1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2015 Chen-Yu Tsai
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Chen-Yu Tsai <wens@csie.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/reset-controller.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/spinlock.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static DEFINE_SPINLOCK(ve_lock);
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define SUN4I_VE_ENABLE 31
19*4882a593Smuzhiyun #define SUN4I_VE_DIVIDER_SHIFT 16
20*4882a593Smuzhiyun #define SUN4I_VE_DIVIDER_WIDTH 3
21*4882a593Smuzhiyun #define SUN4I_VE_RESET 0
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /**
24*4882a593Smuzhiyun * sunxi_ve_reset... - reset bit in ve clk registers handling
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct ve_reset_data {
28*4882a593Smuzhiyun void __iomem *reg;
29*4882a593Smuzhiyun spinlock_t *lock;
30*4882a593Smuzhiyun struct reset_controller_dev rcdev;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
sunxi_ve_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)33*4882a593Smuzhiyun static int sunxi_ve_reset_assert(struct reset_controller_dev *rcdev,
34*4882a593Smuzhiyun unsigned long id)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct ve_reset_data *data = container_of(rcdev,
37*4882a593Smuzhiyun struct ve_reset_data,
38*4882a593Smuzhiyun rcdev);
39*4882a593Smuzhiyun unsigned long flags;
40*4882a593Smuzhiyun u32 reg;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun spin_lock_irqsave(data->lock, flags);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun reg = readl(data->reg);
45*4882a593Smuzhiyun writel(reg & ~BIT(SUN4I_VE_RESET), data->reg);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun spin_unlock_irqrestore(data->lock, flags);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
sunxi_ve_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)52*4882a593Smuzhiyun static int sunxi_ve_reset_deassert(struct reset_controller_dev *rcdev,
53*4882a593Smuzhiyun unsigned long id)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct ve_reset_data *data = container_of(rcdev,
56*4882a593Smuzhiyun struct ve_reset_data,
57*4882a593Smuzhiyun rcdev);
58*4882a593Smuzhiyun unsigned long flags;
59*4882a593Smuzhiyun u32 reg;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun spin_lock_irqsave(data->lock, flags);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun reg = readl(data->reg);
64*4882a593Smuzhiyun writel(reg | BIT(SUN4I_VE_RESET), data->reg);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun spin_unlock_irqrestore(data->lock, flags);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
sunxi_ve_of_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)71*4882a593Smuzhiyun static int sunxi_ve_of_xlate(struct reset_controller_dev *rcdev,
72*4882a593Smuzhiyun const struct of_phandle_args *reset_spec)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun if (WARN_ON(reset_spec->args_count != 0))
75*4882a593Smuzhiyun return -EINVAL;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static const struct reset_control_ops sunxi_ve_reset_ops = {
81*4882a593Smuzhiyun .assert = sunxi_ve_reset_assert,
82*4882a593Smuzhiyun .deassert = sunxi_ve_reset_deassert,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
sun4i_ve_clk_setup(struct device_node * node)85*4882a593Smuzhiyun static void __init sun4i_ve_clk_setup(struct device_node *node)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct clk *clk;
88*4882a593Smuzhiyun struct clk_divider *div;
89*4882a593Smuzhiyun struct clk_gate *gate;
90*4882a593Smuzhiyun struct ve_reset_data *reset_data;
91*4882a593Smuzhiyun const char *parent;
92*4882a593Smuzhiyun const char *clk_name = node->name;
93*4882a593Smuzhiyun void __iomem *reg;
94*4882a593Smuzhiyun int err;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun reg = of_io_request_and_map(node, 0, of_node_full_name(node));
97*4882a593Smuzhiyun if (IS_ERR(reg))
98*4882a593Smuzhiyun return;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun div = kzalloc(sizeof(*div), GFP_KERNEL);
101*4882a593Smuzhiyun if (!div)
102*4882a593Smuzhiyun goto err_unmap;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun gate = kzalloc(sizeof(*gate), GFP_KERNEL);
105*4882a593Smuzhiyun if (!gate)
106*4882a593Smuzhiyun goto err_free_div;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun of_property_read_string(node, "clock-output-names", &clk_name);
109*4882a593Smuzhiyun parent = of_clk_get_parent_name(node, 0);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun gate->reg = reg;
112*4882a593Smuzhiyun gate->bit_idx = SUN4I_VE_ENABLE;
113*4882a593Smuzhiyun gate->lock = &ve_lock;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun div->reg = reg;
116*4882a593Smuzhiyun div->shift = SUN4I_VE_DIVIDER_SHIFT;
117*4882a593Smuzhiyun div->width = SUN4I_VE_DIVIDER_WIDTH;
118*4882a593Smuzhiyun div->lock = &ve_lock;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun clk = clk_register_composite(NULL, clk_name, &parent, 1,
121*4882a593Smuzhiyun NULL, NULL,
122*4882a593Smuzhiyun &div->hw, &clk_divider_ops,
123*4882a593Smuzhiyun &gate->hw, &clk_gate_ops,
124*4882a593Smuzhiyun CLK_SET_RATE_PARENT);
125*4882a593Smuzhiyun if (IS_ERR(clk))
126*4882a593Smuzhiyun goto err_free_gate;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
129*4882a593Smuzhiyun if (err)
130*4882a593Smuzhiyun goto err_unregister_clk;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
133*4882a593Smuzhiyun if (!reset_data)
134*4882a593Smuzhiyun goto err_del_provider;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun reset_data->reg = reg;
137*4882a593Smuzhiyun reset_data->lock = &ve_lock;
138*4882a593Smuzhiyun reset_data->rcdev.nr_resets = 1;
139*4882a593Smuzhiyun reset_data->rcdev.ops = &sunxi_ve_reset_ops;
140*4882a593Smuzhiyun reset_data->rcdev.of_node = node;
141*4882a593Smuzhiyun reset_data->rcdev.of_xlate = sunxi_ve_of_xlate;
142*4882a593Smuzhiyun reset_data->rcdev.of_reset_n_cells = 0;
143*4882a593Smuzhiyun err = reset_controller_register(&reset_data->rcdev);
144*4882a593Smuzhiyun if (err)
145*4882a593Smuzhiyun goto err_free_reset;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun err_free_reset:
150*4882a593Smuzhiyun kfree(reset_data);
151*4882a593Smuzhiyun err_del_provider:
152*4882a593Smuzhiyun of_clk_del_provider(node);
153*4882a593Smuzhiyun err_unregister_clk:
154*4882a593Smuzhiyun clk_unregister(clk);
155*4882a593Smuzhiyun err_free_gate:
156*4882a593Smuzhiyun kfree(gate);
157*4882a593Smuzhiyun err_free_div:
158*4882a593Smuzhiyun kfree(div);
159*4882a593Smuzhiyun err_unmap:
160*4882a593Smuzhiyun iounmap(reg);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun CLK_OF_DECLARE(sun4i_ve, "allwinner,sun4i-a10-ve-clk",
163*4882a593Smuzhiyun sun4i_ve_clk_setup);
164