1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2013 Emilio López
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Emilio López <emilio@elopez.com.ar>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun static DEFINE_SPINLOCK(mod1_lock);
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define SUN4I_MOD1_ENABLE 31
17*4882a593Smuzhiyun #define SUN4I_MOD1_MUX 16
18*4882a593Smuzhiyun #define SUN4I_MOD1_MUX_WIDTH 2
19*4882a593Smuzhiyun #define SUN4I_MOD1_MAX_PARENTS 4
20*4882a593Smuzhiyun
sun4i_mod1_clk_setup(struct device_node * node)21*4882a593Smuzhiyun static void __init sun4i_mod1_clk_setup(struct device_node *node)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct clk *clk;
24*4882a593Smuzhiyun struct clk_mux *mux;
25*4882a593Smuzhiyun struct clk_gate *gate;
26*4882a593Smuzhiyun const char *parents[4];
27*4882a593Smuzhiyun const char *clk_name = node->name;
28*4882a593Smuzhiyun void __iomem *reg;
29*4882a593Smuzhiyun int i;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun reg = of_io_request_and_map(node, 0, of_node_full_name(node));
32*4882a593Smuzhiyun if (IS_ERR(reg))
33*4882a593Smuzhiyun return;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun mux = kzalloc(sizeof(*mux), GFP_KERNEL);
36*4882a593Smuzhiyun if (!mux)
37*4882a593Smuzhiyun goto err_unmap;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun gate = kzalloc(sizeof(*gate), GFP_KERNEL);
40*4882a593Smuzhiyun if (!gate)
41*4882a593Smuzhiyun goto err_free_mux;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun of_property_read_string(node, "clock-output-names", &clk_name);
44*4882a593Smuzhiyun i = of_clk_parent_fill(node, parents, SUN4I_MOD1_MAX_PARENTS);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun gate->reg = reg;
47*4882a593Smuzhiyun gate->bit_idx = SUN4I_MOD1_ENABLE;
48*4882a593Smuzhiyun gate->lock = &mod1_lock;
49*4882a593Smuzhiyun mux->reg = reg;
50*4882a593Smuzhiyun mux->shift = SUN4I_MOD1_MUX;
51*4882a593Smuzhiyun mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
52*4882a593Smuzhiyun mux->lock = &mod1_lock;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun clk = clk_register_composite(NULL, clk_name, parents, i,
55*4882a593Smuzhiyun &mux->hw, &clk_mux_ops,
56*4882a593Smuzhiyun NULL, NULL,
57*4882a593Smuzhiyun &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
58*4882a593Smuzhiyun if (IS_ERR(clk))
59*4882a593Smuzhiyun goto err_free_gate;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun of_clk_add_provider(node, of_clk_src_simple_get, clk);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun err_free_gate:
66*4882a593Smuzhiyun kfree(gate);
67*4882a593Smuzhiyun err_free_mux:
68*4882a593Smuzhiyun kfree(mux);
69*4882a593Smuzhiyun err_unmap:
70*4882a593Smuzhiyun iounmap(reg);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk",
73*4882a593Smuzhiyun sun4i_mod1_clk_setup);
74