1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef _CCU_NKM_H_
7*4882a593Smuzhiyun #define _CCU_NKM_H_
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "ccu_common.h"
12*4882a593Smuzhiyun #include "ccu_div.h"
13*4882a593Smuzhiyun #include "ccu_mult.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun * struct ccu_nkm - Definition of an N-K-M clock
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * Clocks based on the formula parent * N * K / M
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun struct ccu_nkm {
21*4882a593Smuzhiyun u32 enable;
22*4882a593Smuzhiyun u32 lock;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct ccu_mult_internal n;
25*4882a593Smuzhiyun struct ccu_mult_internal k;
26*4882a593Smuzhiyun struct ccu_div_internal m;
27*4882a593Smuzhiyun struct ccu_mux_internal mux;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun unsigned int fixed_post_div;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun struct ccu_common common;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \
35*4882a593Smuzhiyun _nshift, _nwidth, \
36*4882a593Smuzhiyun _kshift, _kwidth, \
37*4882a593Smuzhiyun _mshift, _mwidth, \
38*4882a593Smuzhiyun _muxshift, _muxwidth, \
39*4882a593Smuzhiyun _gate, _lock, _flags) \
40*4882a593Smuzhiyun struct ccu_nkm _struct = { \
41*4882a593Smuzhiyun .enable = _gate, \
42*4882a593Smuzhiyun .lock = _lock, \
43*4882a593Smuzhiyun .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
44*4882a593Smuzhiyun .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
45*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
46*4882a593Smuzhiyun .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
47*4882a593Smuzhiyun .common = { \
48*4882a593Smuzhiyun .reg = _reg, \
49*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_PARENTS(_name, \
50*4882a593Smuzhiyun _parents, \
51*4882a593Smuzhiyun &ccu_nkm_ops, \
52*4882a593Smuzhiyun _flags), \
53*4882a593Smuzhiyun }, \
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
57*4882a593Smuzhiyun _nshift, _nwidth, \
58*4882a593Smuzhiyun _kshift, _kwidth, \
59*4882a593Smuzhiyun _mshift, _mwidth, \
60*4882a593Smuzhiyun _gate, _lock, _flags) \
61*4882a593Smuzhiyun struct ccu_nkm _struct = { \
62*4882a593Smuzhiyun .enable = _gate, \
63*4882a593Smuzhiyun .lock = _lock, \
64*4882a593Smuzhiyun .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
65*4882a593Smuzhiyun .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
66*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
67*4882a593Smuzhiyun .common = { \
68*4882a593Smuzhiyun .reg = _reg, \
69*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
70*4882a593Smuzhiyun _parent, \
71*4882a593Smuzhiyun &ccu_nkm_ops, \
72*4882a593Smuzhiyun _flags), \
73*4882a593Smuzhiyun }, \
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
hw_to_ccu_nkm(struct clk_hw * hw)76*4882a593Smuzhiyun static inline struct ccu_nkm *hw_to_ccu_nkm(struct clk_hw *hw)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct ccu_common *common = hw_to_ccu_common(hw);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return container_of(common, struct ccu_nkm, common);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun extern const struct clk_ops ccu_nkm_ops;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #endif /* _CCU_NKM_H_ */
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