1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef _CCU_MP_H_
7*4882a593Smuzhiyun #define _CCU_MP_H_
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <linux/clk-provider.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "ccu_common.h"
13*4882a593Smuzhiyun #include "ccu_div.h"
14*4882a593Smuzhiyun #include "ccu_mult.h"
15*4882a593Smuzhiyun #include "ccu_mux.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * struct ccu_mp - Definition of an M-P clock
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Clocks based on the formula parent >> P / M
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun struct ccu_mp {
23*4882a593Smuzhiyun u32 enable;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun struct ccu_div_internal m;
26*4882a593Smuzhiyun struct ccu_div_internal p;
27*4882a593Smuzhiyun struct ccu_mux_internal mux;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun unsigned int fixed_post_div;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun struct ccu_common common;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \
35*4882a593Smuzhiyun _mshift, _mwidth, \
36*4882a593Smuzhiyun _pshift, _pwidth, \
37*4882a593Smuzhiyun _muxshift, _muxwidth, \
38*4882a593Smuzhiyun _gate, _postdiv, _flags) \
39*4882a593Smuzhiyun struct ccu_mp _struct = { \
40*4882a593Smuzhiyun .enable = _gate, \
41*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
42*4882a593Smuzhiyun .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
43*4882a593Smuzhiyun .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
44*4882a593Smuzhiyun .fixed_post_div = _postdiv, \
45*4882a593Smuzhiyun .common = { \
46*4882a593Smuzhiyun .reg = _reg, \
47*4882a593Smuzhiyun .features = CCU_FEATURE_FIXED_POSTDIV, \
48*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_PARENTS(_name, \
49*4882a593Smuzhiyun _parents, \
50*4882a593Smuzhiyun &ccu_mp_ops, \
51*4882a593Smuzhiyun _flags), \
52*4882a593Smuzhiyun } \
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
56*4882a593Smuzhiyun _mshift, _mwidth, \
57*4882a593Smuzhiyun _pshift, _pwidth, \
58*4882a593Smuzhiyun _muxshift, _muxwidth, \
59*4882a593Smuzhiyun _gate, _flags) \
60*4882a593Smuzhiyun struct ccu_mp _struct = { \
61*4882a593Smuzhiyun .enable = _gate, \
62*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
63*4882a593Smuzhiyun .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
64*4882a593Smuzhiyun .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
65*4882a593Smuzhiyun .common = { \
66*4882a593Smuzhiyun .reg = _reg, \
67*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_PARENTS(_name, \
68*4882a593Smuzhiyun _parents, \
69*4882a593Smuzhiyun &ccu_mp_ops, \
70*4882a593Smuzhiyun _flags), \
71*4882a593Smuzhiyun } \
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \
75*4882a593Smuzhiyun _mshift, _mwidth, \
76*4882a593Smuzhiyun _pshift, _pwidth, \
77*4882a593Smuzhiyun _muxshift, _muxwidth, \
78*4882a593Smuzhiyun _flags) \
79*4882a593Smuzhiyun SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
80*4882a593Smuzhiyun _mshift, _mwidth, \
81*4882a593Smuzhiyun _pshift, _pwidth, \
82*4882a593Smuzhiyun _muxshift, _muxwidth, \
83*4882a593Smuzhiyun 0, _flags)
84*4882a593Smuzhiyun
hw_to_ccu_mp(struct clk_hw * hw)85*4882a593Smuzhiyun static inline struct ccu_mp *hw_to_ccu_mp(struct clk_hw *hw)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct ccu_common *common = hw_to_ccu_common(hw);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return container_of(common, struct ccu_mp, common);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun extern const struct clk_ops ccu_mp_ops;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /*
95*4882a593Smuzhiyun * Special class of M-P clock that supports MMC timing modes
96*4882a593Smuzhiyun *
97*4882a593Smuzhiyun * Since the MMC clock registers all follow the same layout, we can
98*4882a593Smuzhiyun * simplify the macro for this particular case. In addition, as
99*4882a593Smuzhiyun * switching modes also affects the output clock rate, we need to
100*4882a593Smuzhiyun * have CLK_GET_RATE_NOCACHE for all these types of clocks.
101*4882a593Smuzhiyun */
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
104*4882a593Smuzhiyun _flags) \
105*4882a593Smuzhiyun struct ccu_mp _struct = { \
106*4882a593Smuzhiyun .enable = BIT(31), \
107*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(0, 4), \
108*4882a593Smuzhiyun .p = _SUNXI_CCU_DIV(16, 2), \
109*4882a593Smuzhiyun .mux = _SUNXI_CCU_MUX(24, 2), \
110*4882a593Smuzhiyun .common = { \
111*4882a593Smuzhiyun .reg = _reg, \
112*4882a593Smuzhiyun .features = CCU_FEATURE_MMC_TIMING_SWITCH, \
113*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_PARENTS(_name, \
114*4882a593Smuzhiyun _parents, \
115*4882a593Smuzhiyun &ccu_mp_mmc_ops, \
116*4882a593Smuzhiyun CLK_GET_RATE_NOCACHE | \
117*4882a593Smuzhiyun _flags), \
118*4882a593Smuzhiyun } \
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun extern const struct clk_ops ccu_mp_mmc_ops;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #endif /* _CCU_MP_H_ */
124