1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 Maxime Ripard. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _COMMON_H_ 7*4882a593Smuzhiyun #define _COMMON_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/compiler.h> 10*4882a593Smuzhiyun #include <linux/clk-provider.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CCU_FEATURE_FRACTIONAL BIT(0) 13*4882a593Smuzhiyun #define CCU_FEATURE_VARIABLE_PREDIV BIT(1) 14*4882a593Smuzhiyun #define CCU_FEATURE_FIXED_PREDIV BIT(2) 15*4882a593Smuzhiyun #define CCU_FEATURE_FIXED_POSTDIV BIT(3) 16*4882a593Smuzhiyun #define CCU_FEATURE_ALL_PREDIV BIT(4) 17*4882a593Smuzhiyun #define CCU_FEATURE_LOCK_REG BIT(5) 18*4882a593Smuzhiyun #define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6) 19*4882a593Smuzhiyun #define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* MMC timing mode switch bit */ 22*4882a593Smuzhiyun #define CCU_MMC_NEW_TIMING_MODE BIT(30) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct device_node; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct ccu_common { 27*4882a593Smuzhiyun void __iomem *base; 28*4882a593Smuzhiyun u16 reg; 29*4882a593Smuzhiyun u16 lock_reg; 30*4882a593Smuzhiyun u32 prediv; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun unsigned long features; 33*4882a593Smuzhiyun spinlock_t *lock; 34*4882a593Smuzhiyun struct clk_hw hw; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun hw_to_ccu_common(struct clk_hw * hw)37*4882a593Smuzhiyunstatic inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun return container_of(hw, struct ccu_common, hw); 40*4882a593Smuzhiyun } 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct sunxi_ccu_desc { 43*4882a593Smuzhiyun struct ccu_common **ccu_clks; 44*4882a593Smuzhiyun unsigned long num_ccu_clks; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct clk_hw_onecell_data *hw_clks; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct ccu_reset_map *resets; 49*4882a593Smuzhiyun unsigned long num_resets; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct ccu_pll_nb { 55*4882a593Smuzhiyun struct notifier_block clk_nb; 56*4882a593Smuzhiyun struct ccu_common *common; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun u32 enable; 59*4882a593Smuzhiyun u32 lock; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define to_ccu_pll_nb(_nb) container_of(_nb, struct ccu_pll_nb, clk_nb) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun int sunxi_ccu_probe(struct device_node *node, void __iomem *reg, 67*4882a593Smuzhiyun const struct sunxi_ccu_desc *desc); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* _COMMON_H_ */ 70