1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _CCU_SUNIV_F1C100S_H_ 8*4882a593Smuzhiyun #define _CCU_SUNIV_F1C100S_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <dt-bindings/clock/suniv-ccu-f1c100s.h> 11*4882a593Smuzhiyun #include <dt-bindings/reset/suniv-ccu-f1c100s.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CLK_PLL_CPU 0 14*4882a593Smuzhiyun #define CLK_PLL_AUDIO_BASE 1 15*4882a593Smuzhiyun #define CLK_PLL_AUDIO 2 16*4882a593Smuzhiyun #define CLK_PLL_AUDIO_2X 3 17*4882a593Smuzhiyun #define CLK_PLL_AUDIO_4X 4 18*4882a593Smuzhiyun #define CLK_PLL_AUDIO_8X 5 19*4882a593Smuzhiyun #define CLK_PLL_VIDEO 6 20*4882a593Smuzhiyun #define CLK_PLL_VIDEO_2X 7 21*4882a593Smuzhiyun #define CLK_PLL_VE 8 22*4882a593Smuzhiyun #define CLK_PLL_DDR0 9 23*4882a593Smuzhiyun #define CLK_PLL_PERIPH 10 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* CPU clock is exported */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CLK_AHB 12 28*4882a593Smuzhiyun #define CLK_APB 13 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* All bus gates, DRAM gates and mod clocks are exported */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define CLK_NUMBER (CLK_AVS + 1) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* _CCU_SUNIV_F1C100S_H_ */ 35