1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Chen-Yu Tsai 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Chen-Yu Tsai <wens@csie.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _CCU_SUN9I_A80_H_ 9*4882a593Smuzhiyun #define _CCU_SUN9I_A80_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/clock/sun9i-a80-ccu.h> 12*4882a593Smuzhiyun #include <dt-bindings/reset/sun9i-a80-ccu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CLK_PLL_C0CPUX 0 15*4882a593Smuzhiyun #define CLK_PLL_C1CPUX 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* pll-audio and pll-periph0 are exported to the PRCM block */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CLK_PLL_VE 4 20*4882a593Smuzhiyun #define CLK_PLL_DDR 5 21*4882a593Smuzhiyun #define CLK_PLL_VIDEO0 6 22*4882a593Smuzhiyun #define CLK_PLL_VIDEO1 7 23*4882a593Smuzhiyun #define CLK_PLL_GPU 8 24*4882a593Smuzhiyun #define CLK_PLL_DE 9 25*4882a593Smuzhiyun #define CLK_PLL_ISP 10 26*4882a593Smuzhiyun #define CLK_PLL_PERIPH1 11 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* The CPUX clocks are exported */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CLK_ATB0 14 31*4882a593Smuzhiyun #define CLK_AXI0 15 32*4882a593Smuzhiyun #define CLK_ATB1 16 33*4882a593Smuzhiyun #define CLK_AXI1 17 34*4882a593Smuzhiyun #define CLK_GTBUS 18 35*4882a593Smuzhiyun #define CLK_AHB0 19 36*4882a593Smuzhiyun #define CLK_AHB1 20 37*4882a593Smuzhiyun #define CLK_AHB2 21 38*4882a593Smuzhiyun #define CLK_APB0 22 39*4882a593Smuzhiyun #define CLK_APB1 23 40*4882a593Smuzhiyun #define CLK_CCI400 24 41*4882a593Smuzhiyun #define CLK_ATS 25 42*4882a593Smuzhiyun #define CLK_TRACE 26 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* module clocks and bus gates exported */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CLK_NUMBER (CLK_BUS_UART5 + 1) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* _CCU_SUN9I_A80_H_ */ 49