1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Chen-Yu Tsai 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Chen-Yu Tsai <wens@csie.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _CCU_SUN9I_A80_DE_H_ 9*4882a593Smuzhiyun #define _CCU_SUN9I_A80_DE_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/clock/sun9i-a80-de.h> 12*4882a593Smuzhiyun #include <dt-bindings/reset/sun9i-a80-de.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Intermediary clock dividers are not exported */ 15*4882a593Smuzhiyun #define CLK_FE0_DIV 31 16*4882a593Smuzhiyun #define CLK_FE1_DIV 32 17*4882a593Smuzhiyun #define CLK_FE2_DIV 33 18*4882a593Smuzhiyun #define CLK_BE0_DIV 34 19*4882a593Smuzhiyun #define CLK_BE1_DIV 35 20*4882a593Smuzhiyun #define CLK_BE2_DIV 36 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CLK_NUMBER (CLK_BE2_DIV + 1) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif /* _CCU_SUN9I_A80_DE_H_ */ 25