1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Based on ccu-sun8i-h3.h, which is: 6*4882a593Smuzhiyun * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _CCU_SUN8I_H3_H_ 10*4882a593Smuzhiyun #define _CCU_SUN8I_H3_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-v3s-ccu.h> 13*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-v3s-ccu.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CLK_PLL_CPU 0 16*4882a593Smuzhiyun #define CLK_PLL_AUDIO_BASE 1 17*4882a593Smuzhiyun #define CLK_PLL_AUDIO 2 18*4882a593Smuzhiyun #define CLK_PLL_AUDIO_2X 3 19*4882a593Smuzhiyun #define CLK_PLL_AUDIO_4X 4 20*4882a593Smuzhiyun #define CLK_PLL_AUDIO_8X 5 21*4882a593Smuzhiyun #define CLK_PLL_VIDEO 6 22*4882a593Smuzhiyun #define CLK_PLL_VE 7 23*4882a593Smuzhiyun #define CLK_PLL_DDR0 8 24*4882a593Smuzhiyun #define CLK_PLL_PERIPH0 9 25*4882a593Smuzhiyun #define CLK_PLL_PERIPH0_2X 10 26*4882a593Smuzhiyun #define CLK_PLL_ISP 11 27*4882a593Smuzhiyun #define CLK_PLL_PERIPH1 12 28*4882a593Smuzhiyun /* Reserve one number for not implemented and not used PLL_DDR1 */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* The CPU clock is exported */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define CLK_AXI 15 33*4882a593Smuzhiyun #define CLK_AHB1 16 34*4882a593Smuzhiyun #define CLK_APB1 17 35*4882a593Smuzhiyun #define CLK_APB2 18 36*4882a593Smuzhiyun #define CLK_AHB2 19 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* All the bus gates are exported */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* The first bunch of module clocks are exported */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define CLK_DRAM 58 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* All the DRAM gates are exported */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Some more module clocks are exported */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define CLK_MBUS 72 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* And the GPU module clock is exported */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define CLK_PLL_DDR1 74 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* _CCU_SUN8I_H3_H_ */ 55