1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _CCU_SUN8I_R40_H_ 7*4882a593Smuzhiyun #define _CCU_SUN8I_R40_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-r40-ccu.h> 10*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-r40-ccu.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CLK_OSC_12M 0 13*4882a593Smuzhiyun #define CLK_PLL_CPU 1 14*4882a593Smuzhiyun #define CLK_PLL_AUDIO_BASE 2 15*4882a593Smuzhiyun #define CLK_PLL_AUDIO 3 16*4882a593Smuzhiyun #define CLK_PLL_AUDIO_2X 4 17*4882a593Smuzhiyun #define CLK_PLL_AUDIO_4X 5 18*4882a593Smuzhiyun #define CLK_PLL_AUDIO_8X 6 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* PLL_VIDEO0 is exported */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CLK_PLL_VIDEO0_2X 8 23*4882a593Smuzhiyun #define CLK_PLL_VE 9 24*4882a593Smuzhiyun #define CLK_PLL_DDR0 10 25*4882a593Smuzhiyun #define CLK_PLL_PERIPH0 11 26*4882a593Smuzhiyun #define CLK_PLL_PERIPH0_SATA 12 27*4882a593Smuzhiyun #define CLK_PLL_PERIPH0_2X 13 28*4882a593Smuzhiyun #define CLK_PLL_PERIPH1 14 29*4882a593Smuzhiyun #define CLK_PLL_PERIPH1_2X 15 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* PLL_VIDEO1 is exported */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CLK_PLL_VIDEO1_2X 17 34*4882a593Smuzhiyun #define CLK_PLL_SATA 18 35*4882a593Smuzhiyun #define CLK_PLL_SATA_OUT 19 36*4882a593Smuzhiyun #define CLK_PLL_GPU 20 37*4882a593Smuzhiyun #define CLK_PLL_MIPI 21 38*4882a593Smuzhiyun #define CLK_PLL_DE 22 39*4882a593Smuzhiyun #define CLK_PLL_DDR1 23 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* The CPU clock is exported */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CLK_AXI 25 44*4882a593Smuzhiyun #define CLK_AHB1 26 45*4882a593Smuzhiyun #define CLK_APB1 27 46*4882a593Smuzhiyun #define CLK_APB2 28 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* All the bus gates are exported */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* The first bunch of module clocks are exported */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define CLK_DRAM 132 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* All the DRAM gates are exported */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Some more module clocks are exported */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CLK_NUMBER (CLK_OUTB + 1) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif /* _CCU_SUN8I_R40_H_ */ 61