1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Maxime Ripard 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Maxime Ripard <maxime.ripard@free-electrons.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _CCU_SUN8I_H3_H_ 9*4882a593Smuzhiyun #define _CCU_SUN8I_H3_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-h3-ccu.h> 12*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-h3-ccu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CLK_PLL_CPUX 0 15*4882a593Smuzhiyun #define CLK_PLL_AUDIO_BASE 1 16*4882a593Smuzhiyun #define CLK_PLL_AUDIO 2 17*4882a593Smuzhiyun #define CLK_PLL_AUDIO_2X 3 18*4882a593Smuzhiyun #define CLK_PLL_AUDIO_4X 4 19*4882a593Smuzhiyun #define CLK_PLL_AUDIO_8X 5 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* PLL_VIDEO is exported */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CLK_PLL_VE 7 24*4882a593Smuzhiyun #define CLK_PLL_DDR 8 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* PLL_PERIPH0 exported for PRCM */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CLK_PLL_PERIPH0_2X 10 29*4882a593Smuzhiyun #define CLK_PLL_GPU 11 30*4882a593Smuzhiyun #define CLK_PLL_PERIPH1 12 31*4882a593Smuzhiyun #define CLK_PLL_DE 13 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* The CPUX clock is exported */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CLK_AXI 15 36*4882a593Smuzhiyun #define CLK_AHB1 16 37*4882a593Smuzhiyun #define CLK_APB1 17 38*4882a593Smuzhiyun #define CLK_APB2 18 39*4882a593Smuzhiyun #define CLK_AHB2 19 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* All the bus gates are exported */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* The first bunch of module clocks are exported */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CLK_DRAM 96 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* All the DRAM gates are exported */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Some more module clocks are exported */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CLK_NUMBER_H3 (CLK_GPU + 1) 52*4882a593Smuzhiyun #define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* _CCU_SUN8I_H3_H_ */ 55