xref: /OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2016 Chen-Yu Tsai
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Chen-Yu Tsai <wens@csie.org>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef _CCU_SUN8I_A83T_H_
9*4882a593Smuzhiyun #define _CCU_SUN8I_A83T_H_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-a83t-ccu.h>
12*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-a83t-ccu.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define CLK_PLL_C0CPUX		0
15*4882a593Smuzhiyun #define CLK_PLL_C1CPUX		1
16*4882a593Smuzhiyun #define CLK_PLL_AUDIO		2
17*4882a593Smuzhiyun #define CLK_PLL_VIDEO0		3
18*4882a593Smuzhiyun #define CLK_PLL_VE		4
19*4882a593Smuzhiyun #define CLK_PLL_DDR		5
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* pll-periph is exported to the PRCM block */
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define CLK_PLL_GPU		7
24*4882a593Smuzhiyun #define CLK_PLL_HSIC		8
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /* pll-de is exported for the display engine */
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define CLK_PLL_VIDEO1		10
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /* The CPUX clocks are exported */
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define CLK_AXI0		13
33*4882a593Smuzhiyun #define CLK_AXI1		14
34*4882a593Smuzhiyun #define CLK_AHB1		15
35*4882a593Smuzhiyun #define CLK_AHB2		16
36*4882a593Smuzhiyun #define CLK_APB1		17
37*4882a593Smuzhiyun #define CLK_APB2		18
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /* bus gates exported */
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define CLK_CCI400		58
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /* module and usb clocks exported */
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define CLK_DRAM		82
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* dram gates and more module clocks exported */
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define CLK_MBUS		95
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* more module clocks exported */
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define CLK_NUMBER		(CLK_GPU_HYD + 1)
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #endif /* _CCU_SUN8I_A83T_H_ */
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