1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Maxime Ripard 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Maxime Ripard <maxime.ripard@free-electrons.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _CCU_SUN8I_A23_A33_H_ 9*4882a593Smuzhiyun #define _CCU_SUN8I_A23_A33_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> 12*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CLK_PLL_CPUX 0 15*4882a593Smuzhiyun #define CLK_PLL_AUDIO_BASE 1 16*4882a593Smuzhiyun #define CLK_PLL_AUDIO 2 17*4882a593Smuzhiyun #define CLK_PLL_AUDIO_2X 3 18*4882a593Smuzhiyun #define CLK_PLL_AUDIO_4X 4 19*4882a593Smuzhiyun #define CLK_PLL_AUDIO_8X 5 20*4882a593Smuzhiyun #define CLK_PLL_VIDEO 6 21*4882a593Smuzhiyun #define CLK_PLL_VIDEO_2X 7 22*4882a593Smuzhiyun #define CLK_PLL_VE 8 23*4882a593Smuzhiyun #define CLK_PLL_DDR0 9 24*4882a593Smuzhiyun #define CLK_PLL_PERIPH 10 25*4882a593Smuzhiyun #define CLK_PLL_PERIPH_2X 11 26*4882a593Smuzhiyun #define CLK_PLL_GPU 12 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* The PLL MIPI clock is exported */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CLK_PLL_HSIC 14 31*4882a593Smuzhiyun #define CLK_PLL_DE 15 32*4882a593Smuzhiyun #define CLK_PLL_DDR1 16 33*4882a593Smuzhiyun #define CLK_PLL_DDR 17 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* The CPUX clock is exported */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define CLK_AXI 19 38*4882a593Smuzhiyun #define CLK_AHB1 20 39*4882a593Smuzhiyun #define CLK_APB1 21 40*4882a593Smuzhiyun #define CLK_APB2 22 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* All the bus gates are exported */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* The first part of the mod clocks is exported */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CLK_DRAM 79 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Some more module clocks are exported */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define CLK_MBUS 95 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* And the last module clocks are exported */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define CLK_NUMBER (CLK_ATS + 1) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* _CCU_SUN8I_A23_A33_H_ */ 57