1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Chen-Yu Tsai 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Chen-Yu Tsai <wens@csie.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _CCU_SUN6I_A31_H_ 9*4882a593Smuzhiyun #define _CCU_SUN6I_A31_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/clock/sun6i-a31-ccu.h> 12*4882a593Smuzhiyun #include <dt-bindings/reset/sun6i-a31-ccu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CLK_PLL_CPU 0 15*4882a593Smuzhiyun #define CLK_PLL_AUDIO_BASE 1 16*4882a593Smuzhiyun #define CLK_PLL_AUDIO 2 17*4882a593Smuzhiyun #define CLK_PLL_AUDIO_2X 3 18*4882a593Smuzhiyun #define CLK_PLL_AUDIO_4X 4 19*4882a593Smuzhiyun #define CLK_PLL_AUDIO_8X 5 20*4882a593Smuzhiyun #define CLK_PLL_VIDEO0 6 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* The PLL_VIDEO0_2X clock is exported */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CLK_PLL_VE 8 25*4882a593Smuzhiyun #define CLK_PLL_DDR 9 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* The PLL_PERIPH clock is exported */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define CLK_PLL_PERIPH_2X 11 30*4882a593Smuzhiyun #define CLK_PLL_VIDEO1 12 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* The PLL_VIDEO1_2X clock is exported */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CLK_PLL_GPU 14 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* The PLL_VIDEO1_2X clock is exported */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define CLK_PLL9 16 39*4882a593Smuzhiyun #define CLK_PLL10 17 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* The CPUX clock is exported */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CLK_AXI 19 44*4882a593Smuzhiyun #define CLK_AHB1 20 45*4882a593Smuzhiyun #define CLK_APB1 21 46*4882a593Smuzhiyun #define CLK_APB2 22 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* All the bus gates are exported */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* The first bunch of module clocks are exported */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* EMAC clock is not implemented */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define CLK_MDFS 107 55*4882a593Smuzhiyun #define CLK_SDRAM0 108 56*4882a593Smuzhiyun #define CLK_SDRAM1 109 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* All the DRAM gates are exported */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Some more module clocks are exported */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define CLK_MBUS0 141 63*4882a593Smuzhiyun #define CLK_MBUS1 142 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Some more module clocks and external clock outputs are exported */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CLK_NUMBER (CLK_OUT_C + 1) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* _CCU_SUN6I_A31_H_ */ 70