1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Maxime Ripard 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Maxime Ripard <maxime.ripard@free-electrons.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _CCU_SUN5I_H_ 9*4882a593Smuzhiyun #define _CCU_SUN5I_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/clock/sun5i-ccu.h> 12*4882a593Smuzhiyun #include <dt-bindings/reset/sun5i-ccu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* The HOSC is exported */ 15*4882a593Smuzhiyun #define CLK_PLL_CORE 2 16*4882a593Smuzhiyun #define CLK_PLL_AUDIO_BASE 3 17*4882a593Smuzhiyun #define CLK_PLL_AUDIO 4 18*4882a593Smuzhiyun #define CLK_PLL_AUDIO_2X 5 19*4882a593Smuzhiyun #define CLK_PLL_AUDIO_4X 6 20*4882a593Smuzhiyun #define CLK_PLL_AUDIO_8X 7 21*4882a593Smuzhiyun #define CLK_PLL_VIDEO0 8 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* The PLL_VIDEO0_2X is exported for HDMI */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CLK_PLL_VE 10 26*4882a593Smuzhiyun #define CLK_PLL_DDR_BASE 11 27*4882a593Smuzhiyun #define CLK_PLL_DDR 12 28*4882a593Smuzhiyun #define CLK_PLL_DDR_OTHER 13 29*4882a593Smuzhiyun #define CLK_PLL_PERIPH 14 30*4882a593Smuzhiyun #define CLK_PLL_VIDEO1 15 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* The PLL_VIDEO1_2X is exported for HDMI */ 33*4882a593Smuzhiyun /* The CPU clock is exported */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CLK_AXI 18 36*4882a593Smuzhiyun #define CLK_AHB 19 37*4882a593Smuzhiyun #define CLK_APB0 20 38*4882a593Smuzhiyun #define CLK_APB1 21 39*4882a593Smuzhiyun #define CLK_DRAM_AXI 22 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* AHB gates are exported */ 42*4882a593Smuzhiyun /* APB0 gates are exported */ 43*4882a593Smuzhiyun /* APB1 gates are exported */ 44*4882a593Smuzhiyun /* Modules clocks are exported */ 45*4882a593Smuzhiyun /* USB clocks are exported */ 46*4882a593Smuzhiyun /* GPS clock is exported */ 47*4882a593Smuzhiyun /* DRAM gates are exported */ 48*4882a593Smuzhiyun /* More display modules clocks are exported */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define CLK_TCON_CH1_SCLK 91 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* The rest of the module clocks are exported */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define CLK_NUMBER (CLK_IEP + 1) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* _CCU_SUN5I_H_ */ 57