1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Maxime Ripard 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Maxime Ripard <maxime.ripard@free-electrons.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _CCU_SUN50I_A64_H_ 9*4882a593Smuzhiyun #define _CCU_SUN50I_A64_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/clock/sun50i-a64-ccu.h> 12*4882a593Smuzhiyun #include <dt-bindings/reset/sun50i-a64-ccu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CLK_OSC_12M 0 15*4882a593Smuzhiyun #define CLK_PLL_CPUX 1 16*4882a593Smuzhiyun #define CLK_PLL_AUDIO_BASE 2 17*4882a593Smuzhiyun #define CLK_PLL_AUDIO 3 18*4882a593Smuzhiyun #define CLK_PLL_AUDIO_2X 4 19*4882a593Smuzhiyun #define CLK_PLL_AUDIO_4X 5 20*4882a593Smuzhiyun #define CLK_PLL_AUDIO_8X 6 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* PLL_VIDEO0 exported for HDMI PHY */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CLK_PLL_VIDEO0_2X 8 25*4882a593Smuzhiyun #define CLK_PLL_VE 9 26*4882a593Smuzhiyun #define CLK_PLL_DDR0 10 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* PLL_PERIPH0 exported for PRCM */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CLK_PLL_PERIPH0_2X 12 31*4882a593Smuzhiyun #define CLK_PLL_PERIPH1 13 32*4882a593Smuzhiyun #define CLK_PLL_PERIPH1_2X 14 33*4882a593Smuzhiyun #define CLK_PLL_VIDEO1 15 34*4882a593Smuzhiyun #define CLK_PLL_GPU 16 35*4882a593Smuzhiyun #define CLK_PLL_MIPI 17 36*4882a593Smuzhiyun #define CLK_PLL_HSIC 18 37*4882a593Smuzhiyun #define CLK_PLL_DE 19 38*4882a593Smuzhiyun #define CLK_PLL_DDR1 20 39*4882a593Smuzhiyun #define CLK_AXI 22 40*4882a593Smuzhiyun #define CLK_APB 23 41*4882a593Smuzhiyun #define CLK_AHB1 24 42*4882a593Smuzhiyun #define CLK_APB1 25 43*4882a593Smuzhiyun #define CLK_APB2 26 44*4882a593Smuzhiyun #define CLK_AHB2 27 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* All the bus gates are exported */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* The first bunch of module clocks are exported */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define CLK_USB_OHCI0_12M 90 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define CLK_USB_OHCI1_12M 92 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define CLK_DRAM 94 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* All the DRAM gates are exported */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* And the DSI and GPU module clock is exported */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CLK_NUMBER (CLK_GPU + 1) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif /* _CCU_SUN50I_A64_H_ */ 63