1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _CCU_SUN50I_A100_H_ 7*4882a593Smuzhiyun #define _CCU_SUN50I_A100_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/clock/sun50i-a100-ccu.h> 10*4882a593Smuzhiyun #include <dt-bindings/reset/sun50i-a100-ccu.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CLK_OSC12M 0 13*4882a593Smuzhiyun #define CLK_PLL_CPUX 1 14*4882a593Smuzhiyun #define CLK_PLL_DDR0 2 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* PLL_PERIPH0 exported for PRCM */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CLK_PLL_PERIPH0_2X 4 19*4882a593Smuzhiyun #define CLK_PLL_PERIPH1 5 20*4882a593Smuzhiyun #define CLK_PLL_PERIPH1_2X 6 21*4882a593Smuzhiyun #define CLK_PLL_GPU 7 22*4882a593Smuzhiyun #define CLK_PLL_VIDEO0 8 23*4882a593Smuzhiyun #define CLK_PLL_VIDEO0_2X 9 24*4882a593Smuzhiyun #define CLK_PLL_VIDEO0_4X 10 25*4882a593Smuzhiyun #define CLK_PLL_VIDEO1 11 26*4882a593Smuzhiyun #define CLK_PLL_VIDEO1_2X 12 27*4882a593Smuzhiyun #define CLK_PLL_VIDEO1_4X 13 28*4882a593Smuzhiyun #define CLK_PLL_VIDEO2 14 29*4882a593Smuzhiyun #define CLK_PLL_VIDEO2_2X 15 30*4882a593Smuzhiyun #define CLK_PLL_VIDEO2_4X 16 31*4882a593Smuzhiyun #define CLK_PLL_VIDEO3 17 32*4882a593Smuzhiyun #define CLK_PLL_VIDEO3_2X 18 33*4882a593Smuzhiyun #define CLK_PLL_VIDEO3_4X 19 34*4882a593Smuzhiyun #define CLK_PLL_VE 20 35*4882a593Smuzhiyun #define CLK_PLL_COM 21 36*4882a593Smuzhiyun #define CLK_PLL_COM_AUDIO 22 37*4882a593Smuzhiyun #define CLK_PLL_AUDIO 23 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* CPUX clock exported for DVFS */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CLK_AXI 25 42*4882a593Smuzhiyun #define CLK_CPUX_APB 26 43*4882a593Smuzhiyun #define CLK_PSI_AHB1_AHB2 27 44*4882a593Smuzhiyun #define CLK_AHB3 28 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* APB1 clock exported for PIO */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define CLK_APB2 30 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* All module clocks and bus gates are exported except DRAM */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define CLK_BUS_DRAM 58 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define CLK_NUMBER (CLK_CSI_ISP + 1) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* _CCU_SUN50I_A100_H_ */ 57