1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 Priit Laes 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Priit Laes <plaes@plaes.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _CCU_SUN4I_A10_H_ 9*4882a593Smuzhiyun #define _CCU_SUN4I_A10_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/clock/sun4i-a10-ccu.h> 12*4882a593Smuzhiyun #include <dt-bindings/clock/sun7i-a20-ccu.h> 13*4882a593Smuzhiyun #include <dt-bindings/reset/sun4i-a10-ccu.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* The HOSC is exported */ 16*4882a593Smuzhiyun #define CLK_PLL_CORE 2 17*4882a593Smuzhiyun #define CLK_PLL_AUDIO_BASE 3 18*4882a593Smuzhiyun #define CLK_PLL_AUDIO 4 19*4882a593Smuzhiyun #define CLK_PLL_AUDIO_2X 5 20*4882a593Smuzhiyun #define CLK_PLL_AUDIO_4X 6 21*4882a593Smuzhiyun #define CLK_PLL_AUDIO_8X 7 22*4882a593Smuzhiyun #define CLK_PLL_VIDEO0 8 23*4882a593Smuzhiyun /* The PLL_VIDEO0_2X clock is exported */ 24*4882a593Smuzhiyun #define CLK_PLL_VE 10 25*4882a593Smuzhiyun #define CLK_PLL_DDR_BASE 11 26*4882a593Smuzhiyun #define CLK_PLL_DDR 12 27*4882a593Smuzhiyun #define CLK_PLL_DDR_OTHER 13 28*4882a593Smuzhiyun #define CLK_PLL_PERIPH_BASE 14 29*4882a593Smuzhiyun #define CLK_PLL_PERIPH 15 30*4882a593Smuzhiyun #define CLK_PLL_PERIPH_SATA 16 31*4882a593Smuzhiyun #define CLK_PLL_VIDEO1 17 32*4882a593Smuzhiyun /* The PLL_VIDEO1_2X clock is exported */ 33*4882a593Smuzhiyun #define CLK_PLL_GPU 19 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* The CPU clock is exported */ 36*4882a593Smuzhiyun #define CLK_AXI 21 37*4882a593Smuzhiyun #define CLK_AXI_DRAM 22 38*4882a593Smuzhiyun #define CLK_AHB 23 39*4882a593Smuzhiyun #define CLK_APB0 24 40*4882a593Smuzhiyun #define CLK_APB1 25 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* AHB gates are exported (23..68) */ 43*4882a593Smuzhiyun /* APB0 gates are exported (69..78) */ 44*4882a593Smuzhiyun /* APB1 gates are exported (79..95) */ 45*4882a593Smuzhiyun /* IP module clocks are exported (96..128) */ 46*4882a593Smuzhiyun /* DRAM gates are exported (129..142)*/ 47*4882a593Smuzhiyun /* Media (display engine clocks & etc) are exported (143..169) */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CLK_NUMBER_SUN4I (CLK_MBUS + 1) 50*4882a593Smuzhiyun #define CLK_NUMBER_SUN7I (CLK_OUT_B + 1) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif /* _CCU_SUN4I_A10_H_ */ 53