1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Clock framework definitions for SPEAr platform 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 ST Microelectronics 5*4882a593Smuzhiyun * Viresh Kumar <vireshk@kernel.org> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 8*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 9*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __SPEAR_CLK_H 13*4882a593Smuzhiyun #define __SPEAR_CLK_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <linux/clk-provider.h> 16*4882a593Smuzhiyun #include <linux/spinlock_types.h> 17*4882a593Smuzhiyun #include <linux/types.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Auxiliary Synth clk */ 20*4882a593Smuzhiyun /* Default masks */ 21*4882a593Smuzhiyun #define AUX_EQ_SEL_SHIFT 30 22*4882a593Smuzhiyun #define AUX_EQ_SEL_MASK 1 23*4882a593Smuzhiyun #define AUX_EQ1_SEL 0 24*4882a593Smuzhiyun #define AUX_EQ2_SEL 1 25*4882a593Smuzhiyun #define AUX_XSCALE_SHIFT 16 26*4882a593Smuzhiyun #define AUX_XSCALE_MASK 0xFFF 27*4882a593Smuzhiyun #define AUX_YSCALE_SHIFT 0 28*4882a593Smuzhiyun #define AUX_YSCALE_MASK 0xFFF 29*4882a593Smuzhiyun #define AUX_SYNT_ENB 31 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct aux_clk_masks { 32*4882a593Smuzhiyun u32 eq_sel_mask; 33*4882a593Smuzhiyun u32 eq_sel_shift; 34*4882a593Smuzhiyun u32 eq1_mask; 35*4882a593Smuzhiyun u32 eq2_mask; 36*4882a593Smuzhiyun u32 xscale_sel_mask; 37*4882a593Smuzhiyun u32 xscale_sel_shift; 38*4882a593Smuzhiyun u32 yscale_sel_mask; 39*4882a593Smuzhiyun u32 yscale_sel_shift; 40*4882a593Smuzhiyun u32 enable_bit; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct aux_rate_tbl { 44*4882a593Smuzhiyun u16 xscale; 45*4882a593Smuzhiyun u16 yscale; 46*4882a593Smuzhiyun u8 eq; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun struct clk_aux { 50*4882a593Smuzhiyun struct clk_hw hw; 51*4882a593Smuzhiyun void __iomem *reg; 52*4882a593Smuzhiyun const struct aux_clk_masks *masks; 53*4882a593Smuzhiyun struct aux_rate_tbl *rtbl; 54*4882a593Smuzhiyun u8 rtbl_cnt; 55*4882a593Smuzhiyun spinlock_t *lock; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Fractional Synth clk */ 59*4882a593Smuzhiyun struct frac_rate_tbl { 60*4882a593Smuzhiyun u32 div; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct clk_frac { 64*4882a593Smuzhiyun struct clk_hw hw; 65*4882a593Smuzhiyun void __iomem *reg; 66*4882a593Smuzhiyun struct frac_rate_tbl *rtbl; 67*4882a593Smuzhiyun u8 rtbl_cnt; 68*4882a593Smuzhiyun spinlock_t *lock; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* GPT clk */ 72*4882a593Smuzhiyun struct gpt_rate_tbl { 73*4882a593Smuzhiyun u16 mscale; 74*4882a593Smuzhiyun u16 nscale; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct clk_gpt { 78*4882a593Smuzhiyun struct clk_hw hw; 79*4882a593Smuzhiyun void __iomem *reg; 80*4882a593Smuzhiyun struct gpt_rate_tbl *rtbl; 81*4882a593Smuzhiyun u8 rtbl_cnt; 82*4882a593Smuzhiyun spinlock_t *lock; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* VCO-PLL clk */ 86*4882a593Smuzhiyun struct pll_rate_tbl { 87*4882a593Smuzhiyun u8 mode; 88*4882a593Smuzhiyun u16 m; 89*4882a593Smuzhiyun u8 n; 90*4882a593Smuzhiyun u8 p; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct clk_vco { 94*4882a593Smuzhiyun struct clk_hw hw; 95*4882a593Smuzhiyun void __iomem *mode_reg; 96*4882a593Smuzhiyun void __iomem *cfg_reg; 97*4882a593Smuzhiyun struct pll_rate_tbl *rtbl; 98*4882a593Smuzhiyun u8 rtbl_cnt; 99*4882a593Smuzhiyun spinlock_t *lock; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun struct clk_pll { 103*4882a593Smuzhiyun struct clk_hw hw; 104*4882a593Smuzhiyun struct clk_vco *vco; 105*4882a593Smuzhiyun const char *parent[1]; 106*4882a593Smuzhiyun spinlock_t *lock; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate, 110*4882a593Smuzhiyun int index); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* clk register routines */ 113*4882a593Smuzhiyun struct clk *clk_register_aux(const char *aux_name, const char *gate_name, 114*4882a593Smuzhiyun const char *parent_name, unsigned long flags, void __iomem *reg, 115*4882a593Smuzhiyun const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, 116*4882a593Smuzhiyun u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); 117*4882a593Smuzhiyun struct clk *clk_register_frac(const char *name, const char *parent_name, 118*4882a593Smuzhiyun unsigned long flags, void __iomem *reg, 119*4882a593Smuzhiyun struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); 120*4882a593Smuzhiyun struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned 121*4882a593Smuzhiyun long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 122*4882a593Smuzhiyun rtbl_cnt, spinlock_t *lock); 123*4882a593Smuzhiyun struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, 124*4882a593Smuzhiyun const char *vco_gate_name, const char *parent_name, 125*4882a593Smuzhiyun unsigned long flags, void __iomem *mode_reg, void __iomem 126*4882a593Smuzhiyun *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, 127*4882a593Smuzhiyun spinlock_t *lock, struct clk **pll_clk, 128*4882a593Smuzhiyun struct clk **vco_gate_clk); 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, 131*4882a593Smuzhiyun unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, 132*4882a593Smuzhiyun int *index); 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif /* __SPEAR_CLK_H */ 135