1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2012 ST Microelectronics
3*4882a593Smuzhiyun * Viresh Kumar <vireshk@kernel.org>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
6*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
7*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Auxiliary Synthesizer clock implementation
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define pr_fmt(fmt) "clk-aux-synth: " fmt
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/clk-provider.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/err.h>
18*4882a593Smuzhiyun #include "clk.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * DOC: Auxiliary Synthesizer clock
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Aux synth gives rate for different values of eq, x and y
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Fout from synthesizer can be given from two equations:
26*4882a593Smuzhiyun * Fout1 = (Fin * X/Y)/2 EQ1
27*4882a593Smuzhiyun * Fout2 = Fin * X/Y EQ2
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct aux_clk_masks default_aux_masks = {
33*4882a593Smuzhiyun .eq_sel_mask = AUX_EQ_SEL_MASK,
34*4882a593Smuzhiyun .eq_sel_shift = AUX_EQ_SEL_SHIFT,
35*4882a593Smuzhiyun .eq1_mask = AUX_EQ1_SEL,
36*4882a593Smuzhiyun .eq2_mask = AUX_EQ2_SEL,
37*4882a593Smuzhiyun .xscale_sel_mask = AUX_XSCALE_MASK,
38*4882a593Smuzhiyun .xscale_sel_shift = AUX_XSCALE_SHIFT,
39*4882a593Smuzhiyun .yscale_sel_mask = AUX_YSCALE_MASK,
40*4882a593Smuzhiyun .yscale_sel_shift = AUX_YSCALE_SHIFT,
41*4882a593Smuzhiyun .enable_bit = AUX_SYNT_ENB,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
aux_calc_rate(struct clk_hw * hw,unsigned long prate,int index)44*4882a593Smuzhiyun static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate,
45*4882a593Smuzhiyun int index)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct clk_aux *aux = to_clk_aux(hw);
48*4882a593Smuzhiyun struct aux_rate_tbl *rtbl = aux->rtbl;
49*4882a593Smuzhiyun u8 eq = rtbl[index].eq ? 1 : 2;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return (((prate / 10000) * rtbl[index].xscale) /
52*4882a593Smuzhiyun (rtbl[index].yscale * eq)) * 10000;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
clk_aux_round_rate(struct clk_hw * hw,unsigned long drate,unsigned long * prate)55*4882a593Smuzhiyun static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate,
56*4882a593Smuzhiyun unsigned long *prate)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun struct clk_aux *aux = to_clk_aux(hw);
59*4882a593Smuzhiyun int unused;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return clk_round_rate_index(hw, drate, *prate, aux_calc_rate,
62*4882a593Smuzhiyun aux->rtbl_cnt, &unused);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
clk_aux_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)65*4882a593Smuzhiyun static unsigned long clk_aux_recalc_rate(struct clk_hw *hw,
66*4882a593Smuzhiyun unsigned long parent_rate)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct clk_aux *aux = to_clk_aux(hw);
69*4882a593Smuzhiyun unsigned int num = 1, den = 1, val, eqn;
70*4882a593Smuzhiyun unsigned long flags = 0;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (aux->lock)
73*4882a593Smuzhiyun spin_lock_irqsave(aux->lock, flags);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun val = readl_relaxed(aux->reg);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (aux->lock)
78*4882a593Smuzhiyun spin_unlock_irqrestore(aux->lock, flags);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask;
81*4882a593Smuzhiyun if (eqn == aux->masks->eq1_mask)
82*4882a593Smuzhiyun den = 2;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* calculate numerator */
85*4882a593Smuzhiyun num = (val >> aux->masks->xscale_sel_shift) &
86*4882a593Smuzhiyun aux->masks->xscale_sel_mask;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* calculate denominator */
89*4882a593Smuzhiyun den *= (val >> aux->masks->yscale_sel_shift) &
90*4882a593Smuzhiyun aux->masks->yscale_sel_mask;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (!den)
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return (((parent_rate / 10000) * num) / den) * 10000;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* Configures new clock rate of aux */
clk_aux_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)99*4882a593Smuzhiyun static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate,
100*4882a593Smuzhiyun unsigned long prate)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun struct clk_aux *aux = to_clk_aux(hw);
103*4882a593Smuzhiyun struct aux_rate_tbl *rtbl = aux->rtbl;
104*4882a593Smuzhiyun unsigned long val, flags = 0;
105*4882a593Smuzhiyun int i;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt,
108*4882a593Smuzhiyun &i);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (aux->lock)
111*4882a593Smuzhiyun spin_lock_irqsave(aux->lock, flags);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun val = readl_relaxed(aux->reg) &
114*4882a593Smuzhiyun ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift);
115*4882a593Smuzhiyun val |= (rtbl[i].eq & aux->masks->eq_sel_mask) <<
116*4882a593Smuzhiyun aux->masks->eq_sel_shift;
117*4882a593Smuzhiyun val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift);
118*4882a593Smuzhiyun val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) <<
119*4882a593Smuzhiyun aux->masks->xscale_sel_shift;
120*4882a593Smuzhiyun val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift);
121*4882a593Smuzhiyun val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) <<
122*4882a593Smuzhiyun aux->masks->yscale_sel_shift;
123*4882a593Smuzhiyun writel_relaxed(val, aux->reg);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun if (aux->lock)
126*4882a593Smuzhiyun spin_unlock_irqrestore(aux->lock, flags);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return 0;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static const struct clk_ops clk_aux_ops = {
132*4882a593Smuzhiyun .recalc_rate = clk_aux_recalc_rate,
133*4882a593Smuzhiyun .round_rate = clk_aux_round_rate,
134*4882a593Smuzhiyun .set_rate = clk_aux_set_rate,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
clk_register_aux(const char * aux_name,const char * gate_name,const char * parent_name,unsigned long flags,void __iomem * reg,const struct aux_clk_masks * masks,struct aux_rate_tbl * rtbl,u8 rtbl_cnt,spinlock_t * lock,struct clk ** gate_clk)137*4882a593Smuzhiyun struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
138*4882a593Smuzhiyun const char *parent_name, unsigned long flags, void __iomem *reg,
139*4882a593Smuzhiyun const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
140*4882a593Smuzhiyun u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun struct clk_aux *aux;
143*4882a593Smuzhiyun struct clk_init_data init;
144*4882a593Smuzhiyun struct clk *clk;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
147*4882a593Smuzhiyun pr_err("Invalid arguments passed");
148*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun aux = kzalloc(sizeof(*aux), GFP_KERNEL);
152*4882a593Smuzhiyun if (!aux)
153*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /* struct clk_aux assignments */
156*4882a593Smuzhiyun if (!masks)
157*4882a593Smuzhiyun aux->masks = &default_aux_masks;
158*4882a593Smuzhiyun else
159*4882a593Smuzhiyun aux->masks = masks;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun aux->reg = reg;
162*4882a593Smuzhiyun aux->rtbl = rtbl;
163*4882a593Smuzhiyun aux->rtbl_cnt = rtbl_cnt;
164*4882a593Smuzhiyun aux->lock = lock;
165*4882a593Smuzhiyun aux->hw.init = &init;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun init.name = aux_name;
168*4882a593Smuzhiyun init.ops = &clk_aux_ops;
169*4882a593Smuzhiyun init.flags = flags;
170*4882a593Smuzhiyun init.parent_names = &parent_name;
171*4882a593Smuzhiyun init.num_parents = 1;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun clk = clk_register(NULL, &aux->hw);
174*4882a593Smuzhiyun if (IS_ERR_OR_NULL(clk))
175*4882a593Smuzhiyun goto free_aux;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun if (gate_name) {
178*4882a593Smuzhiyun struct clk *tgate_clk;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun tgate_clk = clk_register_gate(NULL, gate_name, aux_name,
181*4882a593Smuzhiyun CLK_SET_RATE_PARENT, reg,
182*4882a593Smuzhiyun aux->masks->enable_bit, 0, lock);
183*4882a593Smuzhiyun if (IS_ERR_OR_NULL(tgate_clk))
184*4882a593Smuzhiyun goto free_aux;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun if (gate_clk)
187*4882a593Smuzhiyun *gate_clk = tgate_clk;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return clk;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun free_aux:
193*4882a593Smuzhiyun kfree(aux);
194*4882a593Smuzhiyun pr_err("clk register failed\n");
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun return NULL;
197*4882a593Smuzhiyun }
198