1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017, Intel Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __STRATIX10_CLK_H 7*4882a593Smuzhiyun #define __STRATIX10_CLK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct stratix10_clock_data { 10*4882a593Smuzhiyun struct clk_onecell_data clk_data; 11*4882a593Smuzhiyun void __iomem *base; 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct stratix10_pll_clock { 15*4882a593Smuzhiyun unsigned int id; 16*4882a593Smuzhiyun const char *name; 17*4882a593Smuzhiyun const struct clk_parent_data *parent_data; 18*4882a593Smuzhiyun u8 num_parents; 19*4882a593Smuzhiyun unsigned long flags; 20*4882a593Smuzhiyun unsigned long offset; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct stratix10_perip_c_clock { 24*4882a593Smuzhiyun unsigned int id; 25*4882a593Smuzhiyun const char *name; 26*4882a593Smuzhiyun const char *parent_name; 27*4882a593Smuzhiyun const struct clk_parent_data *parent_data; 28*4882a593Smuzhiyun u8 num_parents; 29*4882a593Smuzhiyun unsigned long flags; 30*4882a593Smuzhiyun unsigned long offset; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct stratix10_perip_cnt_clock { 34*4882a593Smuzhiyun unsigned int id; 35*4882a593Smuzhiyun const char *name; 36*4882a593Smuzhiyun const char *parent_name; 37*4882a593Smuzhiyun const struct clk_parent_data *parent_data; 38*4882a593Smuzhiyun u8 num_parents; 39*4882a593Smuzhiyun unsigned long flags; 40*4882a593Smuzhiyun unsigned long offset; 41*4882a593Smuzhiyun u8 fixed_divider; 42*4882a593Smuzhiyun unsigned long bypass_reg; 43*4882a593Smuzhiyun unsigned long bypass_shift; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct stratix10_gate_clock { 47*4882a593Smuzhiyun unsigned int id; 48*4882a593Smuzhiyun const char *name; 49*4882a593Smuzhiyun const char *parent_name; 50*4882a593Smuzhiyun const struct clk_parent_data *parent_data; 51*4882a593Smuzhiyun u8 num_parents; 52*4882a593Smuzhiyun unsigned long flags; 53*4882a593Smuzhiyun unsigned long gate_reg; 54*4882a593Smuzhiyun u8 gate_idx; 55*4882a593Smuzhiyun unsigned long div_reg; 56*4882a593Smuzhiyun u8 div_offset; 57*4882a593Smuzhiyun u8 div_width; 58*4882a593Smuzhiyun unsigned long bypass_reg; 59*4882a593Smuzhiyun u8 bypass_shift; 60*4882a593Smuzhiyun u8 fixed_div; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct clk *s10_register_pll(const struct stratix10_pll_clock *, 64*4882a593Smuzhiyun void __iomem *); 65*4882a593Smuzhiyun struct clk *agilex_register_pll(const struct stratix10_pll_clock *, 66*4882a593Smuzhiyun void __iomem *); 67*4882a593Smuzhiyun struct clk *s10_register_periph(const struct stratix10_perip_c_clock *, 68*4882a593Smuzhiyun void __iomem *); 69*4882a593Smuzhiyun struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *, 70*4882a593Smuzhiyun void __iomem *); 71*4882a593Smuzhiyun struct clk *s10_register_gate(const struct stratix10_gate_clock *, 72*4882a593Smuzhiyun void __iomem *); 73*4882a593Smuzhiyun #endif /* __STRATIX10_CLK_H */ 74