1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * based on drivers/clk/tegra/clk.h 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __SOCFPGA_CLK_H 9*4882a593Smuzhiyun #define __SOCFPGA_CLK_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/clk-provider.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Clock Manager offsets */ 14*4882a593Smuzhiyun #define CLKMGR_CTRL 0x0 15*4882a593Smuzhiyun #define CLKMGR_BYPASS 0x4 16*4882a593Smuzhiyun #define CLKMGR_DBCTRL 0x10 17*4882a593Smuzhiyun #define CLKMGR_L4SRC 0x70 18*4882a593Smuzhiyun #define CLKMGR_PERPLL_SRC 0xAC 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SOCFPGA_MAX_PARENTS 5 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define streq(a, b) (strcmp((a), (b)) == 0) 23*4882a593Smuzhiyun #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ 24*4882a593Smuzhiyun ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \ 27*4882a593Smuzhiyun ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun extern void __iomem *clk_mgr_base_addr; 30*4882a593Smuzhiyun extern void __iomem *clk_mgr_a10_base_addr; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun void __init socfpga_pll_init(struct device_node *node); 33*4882a593Smuzhiyun void __init socfpga_periph_init(struct device_node *node); 34*4882a593Smuzhiyun void __init socfpga_gate_init(struct device_node *node); 35*4882a593Smuzhiyun void socfpga_a10_pll_init(struct device_node *node); 36*4882a593Smuzhiyun void socfpga_a10_periph_init(struct device_node *node); 37*4882a593Smuzhiyun void socfpga_a10_gate_init(struct device_node *node); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct socfpga_pll { 40*4882a593Smuzhiyun struct clk_gate hw; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct socfpga_gate_clk { 44*4882a593Smuzhiyun struct clk_gate hw; 45*4882a593Smuzhiyun char *parent_name; 46*4882a593Smuzhiyun u32 fixed_div; 47*4882a593Smuzhiyun void __iomem *div_reg; 48*4882a593Smuzhiyun void __iomem *bypass_reg; 49*4882a593Smuzhiyun struct regmap *sys_mgr_base_addr; 50*4882a593Smuzhiyun u32 width; /* only valid if div_reg != 0 */ 51*4882a593Smuzhiyun u32 shift; /* only valid if div_reg != 0 */ 52*4882a593Smuzhiyun u32 bypass_shift; /* only valid if bypass_reg != 0 */ 53*4882a593Smuzhiyun u32 clk_phase[2]; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct socfpga_periph_clk { 57*4882a593Smuzhiyun struct clk_gate hw; 58*4882a593Smuzhiyun char *parent_name; 59*4882a593Smuzhiyun u32 fixed_div; 60*4882a593Smuzhiyun void __iomem *div_reg; 61*4882a593Smuzhiyun void __iomem *bypass_reg; 62*4882a593Smuzhiyun u32 width; /* only valid if div_reg != 0 */ 63*4882a593Smuzhiyun u32 shift; /* only valid if div_reg != 0 */ 64*4882a593Smuzhiyun u32 bypass_shift; /* only valid if bypass_reg != 0 */ 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* SOCFPGA_CLK_H */ 68