1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2011-2012 Calxeda, Inc. 4*4882a593Smuzhiyun * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based from clk-highbank.c 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #include <linux/of.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "clk.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun CLK_OF_DECLARE(socfpga_pll_clk, "altr,socfpga-pll-clock", socfpga_pll_init); 13*4882a593Smuzhiyun CLK_OF_DECLARE(socfpga_perip_clk, "altr,socfpga-perip-clk", socfpga_periph_init); 14*4882a593Smuzhiyun CLK_OF_DECLARE(socfpga_gate_clk, "altr,socfpga-gate-clk", socfpga_gate_init); 15*4882a593Smuzhiyun CLK_OF_DECLARE(socfpga_a10_pll_clk, "altr,socfpga-a10-pll-clock", 16*4882a593Smuzhiyun socfpga_a10_pll_init); 17*4882a593Smuzhiyun CLK_OF_DECLARE(socfpga_a10_perip_clk, "altr,socfpga-a10-perip-clk", 18*4882a593Smuzhiyun socfpga_a10_periph_init); 19*4882a593Smuzhiyun CLK_OF_DECLARE(socfpga_a10_gate_clk, "altr,socfpga-a10-gate-clk", 20*4882a593Smuzhiyun socfpga_a10_gate_init); 21