1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2017, Intel Corporation
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include <linux/clk-provider.h>
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun #include <linux/slab.h>
8*4882a593Smuzhiyun #include "stratix10-clk.h"
9*4882a593Smuzhiyun #include "clk.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
12*4882a593Smuzhiyun #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
13*4882a593Smuzhiyun
socfpga_gate_clk_recalc_rate(struct clk_hw * hwclk,unsigned long parent_rate)14*4882a593Smuzhiyun static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
15*4882a593Smuzhiyun unsigned long parent_rate)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
18*4882a593Smuzhiyun u32 div = 1, val;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun if (socfpgaclk->fixed_div) {
21*4882a593Smuzhiyun div = socfpgaclk->fixed_div;
22*4882a593Smuzhiyun } else if (socfpgaclk->div_reg) {
23*4882a593Smuzhiyun val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
24*4882a593Smuzhiyun val &= GENMASK(socfpgaclk->width - 1, 0);
25*4882a593Smuzhiyun div = (1 << val);
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun return parent_rate / div;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
socfpga_dbg_clk_recalc_rate(struct clk_hw * hwclk,unsigned long parent_rate)30*4882a593Smuzhiyun static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
31*4882a593Smuzhiyun unsigned long parent_rate)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
34*4882a593Smuzhiyun u32 div = 1, val;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
37*4882a593Smuzhiyun val &= GENMASK(socfpgaclk->width - 1, 0);
38*4882a593Smuzhiyun div = (1 << val);
39*4882a593Smuzhiyun div = div ? 4 : 1;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return parent_rate / div;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
socfpga_gate_get_parent(struct clk_hw * hwclk)44*4882a593Smuzhiyun static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
47*4882a593Smuzhiyun u32 mask;
48*4882a593Smuzhiyun u8 parent = 0;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if (socfpgaclk->bypass_reg) {
51*4882a593Smuzhiyun mask = (0x1 << socfpgaclk->bypass_shift);
52*4882a593Smuzhiyun parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
53*4882a593Smuzhiyun socfpgaclk->bypass_shift);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun return parent;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static struct clk_ops gateclk_ops = {
59*4882a593Smuzhiyun .recalc_rate = socfpga_gate_clk_recalc_rate,
60*4882a593Smuzhiyun .get_parent = socfpga_gate_get_parent,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static const struct clk_ops dbgclk_ops = {
64*4882a593Smuzhiyun .recalc_rate = socfpga_dbg_clk_recalc_rate,
65*4882a593Smuzhiyun .get_parent = socfpga_gate_get_parent,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
s10_register_gate(const struct stratix10_gate_clock * clks,void __iomem * regbase)68*4882a593Smuzhiyun struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct clk *clk;
71*4882a593Smuzhiyun struct socfpga_gate_clk *socfpga_clk;
72*4882a593Smuzhiyun struct clk_init_data init;
73*4882a593Smuzhiyun const char *parent_name = clks->parent_name;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
76*4882a593Smuzhiyun if (!socfpga_clk)
77*4882a593Smuzhiyun return NULL;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun socfpga_clk->hw.reg = regbase + clks->gate_reg;
80*4882a593Smuzhiyun socfpga_clk->hw.bit_idx = clks->gate_idx;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun gateclk_ops.enable = clk_gate_ops.enable;
83*4882a593Smuzhiyun gateclk_ops.disable = clk_gate_ops.disable;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun socfpga_clk->fixed_div = clks->fixed_div;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (clks->div_reg)
88*4882a593Smuzhiyun socfpga_clk->div_reg = regbase + clks->div_reg;
89*4882a593Smuzhiyun else
90*4882a593Smuzhiyun socfpga_clk->div_reg = NULL;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun socfpga_clk->width = clks->div_width;
93*4882a593Smuzhiyun socfpga_clk->shift = clks->div_offset;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun if (clks->bypass_reg)
96*4882a593Smuzhiyun socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
97*4882a593Smuzhiyun else
98*4882a593Smuzhiyun socfpga_clk->bypass_reg = NULL;
99*4882a593Smuzhiyun socfpga_clk->bypass_shift = clks->bypass_shift;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (streq(clks->name, "cs_pdbg_clk"))
102*4882a593Smuzhiyun init.ops = &dbgclk_ops;
103*4882a593Smuzhiyun else
104*4882a593Smuzhiyun init.ops = &gateclk_ops;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun init.name = clks->name;
107*4882a593Smuzhiyun init.flags = clks->flags;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun init.num_parents = clks->num_parents;
110*4882a593Smuzhiyun init.parent_names = parent_name ? &parent_name : NULL;
111*4882a593Smuzhiyun if (init.parent_names == NULL)
112*4882a593Smuzhiyun init.parent_data = clks->parent_data;
113*4882a593Smuzhiyun socfpga_clk->hw.hw.init = &init;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun clk = clk_register(NULL, &socfpga_clk->hw.hw);
116*4882a593Smuzhiyun if (WARN_ON(IS_ERR(clk))) {
117*4882a593Smuzhiyun kfree(socfpga_clk);
118*4882a593Smuzhiyun return NULL;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun return clk;
121*4882a593Smuzhiyun }
122