1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #define SIRFSOC_CLKC_CLK_EN0 0x0000 3*4882a593Smuzhiyun #define SIRFSOC_CLKC_CLK_EN1 0x0004 4*4882a593Smuzhiyun #define SIRFSOC_CLKC_REF_CFG 0x0014 5*4882a593Smuzhiyun #define SIRFSOC_CLKC_CPU_CFG 0x0018 6*4882a593Smuzhiyun #define SIRFSOC_CLKC_MEM_CFG 0x001c 7*4882a593Smuzhiyun #define SIRFSOC_CLKC_SYS_CFG 0x0020 8*4882a593Smuzhiyun #define SIRFSOC_CLKC_IO_CFG 0x0024 9*4882a593Smuzhiyun #define SIRFSOC_CLKC_DSP_CFG 0x0028 10*4882a593Smuzhiyun #define SIRFSOC_CLKC_GFX_CFG 0x002c 11*4882a593Smuzhiyun #define SIRFSOC_CLKC_MM_CFG 0x0030 12*4882a593Smuzhiyun #define SIRFSOC_CLKC_LCD_CFG 0x0034 13*4882a593Smuzhiyun #define SIRFSOC_CLKC_MMC_CFG 0x0038 14*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL1_CFG0 0x0040 15*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL2_CFG0 0x0044 16*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL3_CFG0 0x0048 17*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL1_CFG1 0x004c 18*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL2_CFG1 0x0050 19*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL3_CFG1 0x0054 20*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL1_CFG2 0x0058 21*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL2_CFG2 0x005c 22*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL3_CFG2 0x0060 23*4882a593Smuzhiyun #define SIRFSOC_USBPHY_PLL_CTRL 0x0008 24*4882a593Smuzhiyun #define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1) 25*4882a593Smuzhiyun #define SIRFSOC_USBPHY_PLL_BYPASS BIT(2) 26*4882a593Smuzhiyun #define SIRFSOC_USBPHY_PLL_LOCK BIT(3) 27