1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Clock tree for CSR SiRFatlasVI
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
6*4882a593Smuzhiyun * company.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/bitops.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/clkdev.h>
13*4882a593Smuzhiyun #include <linux/clk-provider.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <linux/syscore_ops.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "atlas6.h"
18*4882a593Smuzhiyun #include "clk-common.c"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static struct clk_dmn clk_mmc01 = {
21*4882a593Smuzhiyun .regofs = SIRFSOC_CLKC_MMC01_CFG,
22*4882a593Smuzhiyun .enable_bit = 59,
23*4882a593Smuzhiyun .hw = {
24*4882a593Smuzhiyun .init = &clk_mmc01_init,
25*4882a593Smuzhiyun },
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static struct clk_dmn clk_mmc23 = {
29*4882a593Smuzhiyun .regofs = SIRFSOC_CLKC_MMC23_CFG,
30*4882a593Smuzhiyun .enable_bit = 60,
31*4882a593Smuzhiyun .hw = {
32*4882a593Smuzhiyun .init = &clk_mmc23_init,
33*4882a593Smuzhiyun },
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static struct clk_dmn clk_mmc45 = {
37*4882a593Smuzhiyun .regofs = SIRFSOC_CLKC_MMC45_CFG,
38*4882a593Smuzhiyun .enable_bit = 61,
39*4882a593Smuzhiyun .hw = {
40*4882a593Smuzhiyun .init = &clk_mmc45_init,
41*4882a593Smuzhiyun },
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static const struct clk_init_data clk_nand_init = {
45*4882a593Smuzhiyun .name = "nand",
46*4882a593Smuzhiyun .ops = &dmn_ops,
47*4882a593Smuzhiyun .parent_names = dmn_clk_parents,
48*4882a593Smuzhiyun .num_parents = ARRAY_SIZE(dmn_clk_parents),
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static struct clk_dmn clk_nand = {
52*4882a593Smuzhiyun .regofs = SIRFSOC_CLKC_NAND_CFG,
53*4882a593Smuzhiyun .enable_bit = 34,
54*4882a593Smuzhiyun .hw = {
55*4882a593Smuzhiyun .init = &clk_nand_init,
56*4882a593Smuzhiyun },
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun enum atlas6_clk_index {
60*4882a593Smuzhiyun /* 0 1 2 3 4 5 6 7 8 9 */
61*4882a593Smuzhiyun rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
62*4882a593Smuzhiyun mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
63*4882a593Smuzhiyun spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
64*4882a593Smuzhiyun usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
65*4882a593Smuzhiyun usb0, usb1, cphif, maxclk,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = {
69*4882a593Smuzhiyun NULL, /* dummy */
70*4882a593Smuzhiyun NULL,
71*4882a593Smuzhiyun &clk_pll1.hw,
72*4882a593Smuzhiyun &clk_pll2.hw,
73*4882a593Smuzhiyun &clk_pll3.hw,
74*4882a593Smuzhiyun &clk_mem.hw,
75*4882a593Smuzhiyun &clk_sys.hw,
76*4882a593Smuzhiyun &clk_security.hw,
77*4882a593Smuzhiyun &clk_dsp.hw,
78*4882a593Smuzhiyun &clk_gps.hw,
79*4882a593Smuzhiyun &clk_mf.hw,
80*4882a593Smuzhiyun &clk_io.hw,
81*4882a593Smuzhiyun &clk_cpu.hw,
82*4882a593Smuzhiyun &clk_uart0.hw,
83*4882a593Smuzhiyun &clk_uart1.hw,
84*4882a593Smuzhiyun &clk_uart2.hw,
85*4882a593Smuzhiyun &clk_tsc.hw,
86*4882a593Smuzhiyun &clk_i2c0.hw,
87*4882a593Smuzhiyun &clk_i2c1.hw,
88*4882a593Smuzhiyun &clk_spi0.hw,
89*4882a593Smuzhiyun &clk_spi1.hw,
90*4882a593Smuzhiyun &clk_pwmc.hw,
91*4882a593Smuzhiyun &clk_efuse.hw,
92*4882a593Smuzhiyun &clk_pulse.hw,
93*4882a593Smuzhiyun &clk_dmac0.hw,
94*4882a593Smuzhiyun &clk_dmac1.hw,
95*4882a593Smuzhiyun &clk_nand.hw,
96*4882a593Smuzhiyun &clk_audio.hw,
97*4882a593Smuzhiyun &clk_usp0.hw,
98*4882a593Smuzhiyun &clk_usp1.hw,
99*4882a593Smuzhiyun &clk_usp2.hw,
100*4882a593Smuzhiyun &clk_vip.hw,
101*4882a593Smuzhiyun &clk_gfx.hw,
102*4882a593Smuzhiyun &clk_gfx2d.hw,
103*4882a593Smuzhiyun &clk_lcd.hw,
104*4882a593Smuzhiyun &clk_vpp.hw,
105*4882a593Smuzhiyun &clk_mmc01.hw,
106*4882a593Smuzhiyun &clk_mmc23.hw,
107*4882a593Smuzhiyun &clk_mmc45.hw,
108*4882a593Smuzhiyun &usb_pll_clk_hw,
109*4882a593Smuzhiyun &clk_usb0.hw,
110*4882a593Smuzhiyun &clk_usb1.hw,
111*4882a593Smuzhiyun &clk_cphif.hw,
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static struct clk *atlas6_clks[maxclk];
115*4882a593Smuzhiyun
atlas6_clk_init(struct device_node * np)116*4882a593Smuzhiyun static void __init atlas6_clk_init(struct device_node *np)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun struct device_node *rscnp;
119*4882a593Smuzhiyun int i;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
122*4882a593Smuzhiyun sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
123*4882a593Smuzhiyun if (!sirfsoc_rsc_vbase)
124*4882a593Smuzhiyun panic("unable to map rsc registers\n");
125*4882a593Smuzhiyun of_node_put(rscnp);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun sirfsoc_clk_vbase = of_iomap(np, 0);
128*4882a593Smuzhiyun if (!sirfsoc_clk_vbase)
129*4882a593Smuzhiyun panic("unable to map clkc registers\n");
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* These are always available (RTC and 26MHz OSC)*/
132*4882a593Smuzhiyun atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
133*4882a593Smuzhiyun atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0,
134*4882a593Smuzhiyun 26000000);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun for (i = pll1; i < maxclk; i++) {
137*4882a593Smuzhiyun atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]);
138*4882a593Smuzhiyun BUG_ON(IS_ERR(atlas6_clks[i]));
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu");
141*4882a593Smuzhiyun clk_register_clkdev(atlas6_clks[io], NULL, "io");
142*4882a593Smuzhiyun clk_register_clkdev(atlas6_clks[mem], NULL, "mem");
143*4882a593Smuzhiyun clk_register_clkdev(atlas6_clks[mem], NULL, "osc");
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun clk_data.clks = atlas6_clks;
146*4882a593Smuzhiyun clk_data.clk_num = maxclk;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init);
151