1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #define SIRFSOC_CLKC_CLK_EN0 0x0000 3*4882a593Smuzhiyun #define SIRFSOC_CLKC_CLK_EN1 0x0004 4*4882a593Smuzhiyun #define SIRFSOC_CLKC_REF_CFG 0x0020 5*4882a593Smuzhiyun #define SIRFSOC_CLKC_CPU_CFG 0x0024 6*4882a593Smuzhiyun #define SIRFSOC_CLKC_MEM_CFG 0x0028 7*4882a593Smuzhiyun #define SIRFSOC_CLKC_MEMDIV_CFG 0x002C 8*4882a593Smuzhiyun #define SIRFSOC_CLKC_SYS_CFG 0x0030 9*4882a593Smuzhiyun #define SIRFSOC_CLKC_IO_CFG 0x0034 10*4882a593Smuzhiyun #define SIRFSOC_CLKC_DSP_CFG 0x0038 11*4882a593Smuzhiyun #define SIRFSOC_CLKC_GFX_CFG 0x003c 12*4882a593Smuzhiyun #define SIRFSOC_CLKC_MM_CFG 0x0040 13*4882a593Smuzhiyun #define SIRFSOC_CLKC_GFX2D_CFG 0x0040 14*4882a593Smuzhiyun #define SIRFSOC_CLKC_LCD_CFG 0x0044 15*4882a593Smuzhiyun #define SIRFSOC_CLKC_MMC01_CFG 0x0048 16*4882a593Smuzhiyun #define SIRFSOC_CLKC_MMC23_CFG 0x004C 17*4882a593Smuzhiyun #define SIRFSOC_CLKC_MMC45_CFG 0x0050 18*4882a593Smuzhiyun #define SIRFSOC_CLKC_NAND_CFG 0x0054 19*4882a593Smuzhiyun #define SIRFSOC_CLKC_NANDDIV_CFG 0x0058 20*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL1_CFG0 0x0080 21*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL2_CFG0 0x0084 22*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL3_CFG0 0x0088 23*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL1_CFG1 0x008c 24*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL2_CFG1 0x0090 25*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL3_CFG1 0x0094 26*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL1_CFG2 0x0098 27*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL2_CFG2 0x009c 28*4882a593Smuzhiyun #define SIRFSOC_CLKC_PLL3_CFG2 0x00A0 29*4882a593Smuzhiyun #define SIRFSOC_USBPHY_PLL_CTRL 0x0008 30*4882a593Smuzhiyun #define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1) 31*4882a593Smuzhiyun #define SIRFSOC_USBPHY_PLL_BYPASS BIT(2) 32*4882a593Smuzhiyun #define SIRFSOC_USBPHY_PLL_LOCK BIT(3) 33