1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * Copyright (c) 2013 Linaro Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Common Clock Framework support for all PLL's in Samsung platforms 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __SAMSUNG_CLK_PLL_H 10*4882a593Smuzhiyun #define __SAMSUNG_CLK_PLL_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun enum samsung_pll_type { 13*4882a593Smuzhiyun pll_2126, 14*4882a593Smuzhiyun pll_3000, 15*4882a593Smuzhiyun pll_35xx, 16*4882a593Smuzhiyun pll_36xx, 17*4882a593Smuzhiyun pll_2550, 18*4882a593Smuzhiyun pll_2650, 19*4882a593Smuzhiyun pll_4500, 20*4882a593Smuzhiyun pll_4502, 21*4882a593Smuzhiyun pll_4508, 22*4882a593Smuzhiyun pll_4600, 23*4882a593Smuzhiyun pll_4650, 24*4882a593Smuzhiyun pll_4650c, 25*4882a593Smuzhiyun pll_6552, 26*4882a593Smuzhiyun pll_6552_s3c2416, 27*4882a593Smuzhiyun pll_6553, 28*4882a593Smuzhiyun pll_s3c2410_mpll, 29*4882a593Smuzhiyun pll_s3c2410_upll, 30*4882a593Smuzhiyun pll_s3c2440_mpll, 31*4882a593Smuzhiyun pll_2550x, 32*4882a593Smuzhiyun pll_2550xx, 33*4882a593Smuzhiyun pll_2650x, 34*4882a593Smuzhiyun pll_2650xx, 35*4882a593Smuzhiyun pll_1450x, 36*4882a593Smuzhiyun pll_1451x, 37*4882a593Smuzhiyun pll_1452x, 38*4882a593Smuzhiyun pll_1460x, 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ 42*4882a593Smuzhiyun ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s))) 43*4882a593Smuzhiyun #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \ 44*4882a593Smuzhiyun BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout))) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \ 47*4882a593Smuzhiyun { \ 48*4882a593Smuzhiyun .rate = PLL_VALID_RATE(_fin, _rate, \ 49*4882a593Smuzhiyun _m, _p, _s, 0, 16), \ 50*4882a593Smuzhiyun .mdiv = (_m), \ 51*4882a593Smuzhiyun .pdiv = (_p), \ 52*4882a593Smuzhiyun .sdiv = (_s), \ 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \ 56*4882a593Smuzhiyun { \ 57*4882a593Smuzhiyun .rate = PLL_VALID_RATE(_fin, _rate, \ 58*4882a593Smuzhiyun _m + 8, _p + 2, _s, 0, 16), \ 59*4882a593Smuzhiyun .mdiv = (_m), \ 60*4882a593Smuzhiyun .pdiv = (_p), \ 61*4882a593Smuzhiyun .sdiv = (_s), \ 62*4882a593Smuzhiyun } 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \ 65*4882a593Smuzhiyun { \ 66*4882a593Smuzhiyun .rate = PLL_VALID_RATE(_fin, _rate, \ 67*4882a593Smuzhiyun 2 * (_m + 8), _p + 2, _s, 0, 16), \ 68*4882a593Smuzhiyun .mdiv = (_m), \ 69*4882a593Smuzhiyun .pdiv = (_p), \ 70*4882a593Smuzhiyun .sdiv = (_s), \ 71*4882a593Smuzhiyun } 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \ 74*4882a593Smuzhiyun { \ 75*4882a593Smuzhiyun .rate = PLL_VALID_RATE(_fin, _rate, \ 76*4882a593Smuzhiyun _m, _p, _s, _k, 16), \ 77*4882a593Smuzhiyun .mdiv = (_m), \ 78*4882a593Smuzhiyun .pdiv = (_p), \ 79*4882a593Smuzhiyun .sdiv = (_s), \ 80*4882a593Smuzhiyun .kdiv = (_k), \ 81*4882a593Smuzhiyun } 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \ 84*4882a593Smuzhiyun { \ 85*4882a593Smuzhiyun .rate = PLL_VALID_RATE(_fin, _rate, \ 86*4882a593Smuzhiyun _m, _p, _s - 1, 0, 16), \ 87*4882a593Smuzhiyun .mdiv = (_m), \ 88*4882a593Smuzhiyun .pdiv = (_p), \ 89*4882a593Smuzhiyun .sdiv = (_s), \ 90*4882a593Smuzhiyun .afc = (_afc), \ 91*4882a593Smuzhiyun } 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \ 94*4882a593Smuzhiyun { \ 95*4882a593Smuzhiyun .rate = PLL_VALID_RATE(_fin, _rate, \ 96*4882a593Smuzhiyun _m, _p, _s, _k, 16), \ 97*4882a593Smuzhiyun .mdiv = (_m), \ 98*4882a593Smuzhiyun .pdiv = (_p), \ 99*4882a593Smuzhiyun .sdiv = (_s), \ 100*4882a593Smuzhiyun .kdiv = (_k), \ 101*4882a593Smuzhiyun .vsel = (_vsel), \ 102*4882a593Smuzhiyun } 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \ 105*4882a593Smuzhiyun { \ 106*4882a593Smuzhiyun .rate = PLL_VALID_RATE(_fin, _rate, \ 107*4882a593Smuzhiyun _m, _p, _s, _k, 10), \ 108*4882a593Smuzhiyun .mdiv = (_m), \ 109*4882a593Smuzhiyun .pdiv = (_p), \ 110*4882a593Smuzhiyun .sdiv = (_s), \ 111*4882a593Smuzhiyun .kdiv = (_k), \ 112*4882a593Smuzhiyun .mfr = (_mfr), \ 113*4882a593Smuzhiyun .mrr = (_mrr), \ 114*4882a593Smuzhiyun .vsel = (_vsel), \ 115*4882a593Smuzhiyun } 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* NOTE: Rate table should be kept sorted in descending order. */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun struct samsung_pll_rate_table { 120*4882a593Smuzhiyun unsigned int rate; 121*4882a593Smuzhiyun unsigned int pdiv; 122*4882a593Smuzhiyun unsigned int mdiv; 123*4882a593Smuzhiyun unsigned int sdiv; 124*4882a593Smuzhiyun unsigned int kdiv; 125*4882a593Smuzhiyun unsigned int afc; 126*4882a593Smuzhiyun unsigned int mfr; 127*4882a593Smuzhiyun unsigned int mrr; 128*4882a593Smuzhiyun unsigned int vsel; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif /* __SAMSUNG_CLK_PLL_H */ 132