1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Common Clock Framework support for all PLL's in Samsung platforms 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __SAMSUNG_CLK_CPU_H 9*4882a593Smuzhiyun #define __SAMSUNG_CLK_CPU_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "clk.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /** 14*4882a593Smuzhiyun * struct exynos_cpuclk_data: config data to setup cpu clocks. 15*4882a593Smuzhiyun * @prate: frequency of the primary parent clock (in KHz). 16*4882a593Smuzhiyun * @div0: value to be programmed in the div_cpu0 register. 17*4882a593Smuzhiyun * @div1: value to be programmed in the div_cpu1 register. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * This structure holds the divider configuration data for dividers in the CPU 20*4882a593Smuzhiyun * clock domain. The parent frequency at which these divider values are valid is 21*4882a593Smuzhiyun * specified in @prate. The @prate is the frequency of the primary parent clock. 22*4882a593Smuzhiyun * For CPU clock domains that do not have a DIV1 register, the @div1 member 23*4882a593Smuzhiyun * value is not used. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun struct exynos_cpuclk_cfg_data { 26*4882a593Smuzhiyun unsigned long prate; 27*4882a593Smuzhiyun unsigned long div0; 28*4882a593Smuzhiyun unsigned long div1; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /** 32*4882a593Smuzhiyun * struct exynos_cpuclk: information about clock supplied to a CPU core. 33*4882a593Smuzhiyun * @hw: handle between CCF and CPU clock. 34*4882a593Smuzhiyun * @alt_parent: alternate parent clock to use when switching the speed 35*4882a593Smuzhiyun * of the primary parent clock. 36*4882a593Smuzhiyun * @ctrl_base: base address of the clock controller. 37*4882a593Smuzhiyun * @lock: cpu clock domain register access lock. 38*4882a593Smuzhiyun * @cfg: cpu clock rate configuration data. 39*4882a593Smuzhiyun * @num_cfgs: number of array elements in @cfg array. 40*4882a593Smuzhiyun * @clk_nb: clock notifier registered for changes in clock speed of the 41*4882a593Smuzhiyun * primary parent clock. 42*4882a593Smuzhiyun * @flags: configuration flags for the CPU clock. 43*4882a593Smuzhiyun * 44*4882a593Smuzhiyun * This structure holds information required for programming the CPU clock for 45*4882a593Smuzhiyun * various clock speeds. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun struct exynos_cpuclk { 48*4882a593Smuzhiyun struct clk_hw hw; 49*4882a593Smuzhiyun const struct clk_hw *alt_parent; 50*4882a593Smuzhiyun void __iomem *ctrl_base; 51*4882a593Smuzhiyun spinlock_t *lock; 52*4882a593Smuzhiyun const struct exynos_cpuclk_cfg_data *cfg; 53*4882a593Smuzhiyun const unsigned long num_cfgs; 54*4882a593Smuzhiyun struct notifier_block clk_nb; 55*4882a593Smuzhiyun unsigned long flags; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* The CPU clock registers have DIV1 configuration register */ 58*4882a593Smuzhiyun #define CLK_CPU_HAS_DIV1 (1 << 0) 59*4882a593Smuzhiyun /* When ALT parent is active, debug clocks need safe divider values */ 60*4882a593Smuzhiyun #define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) 61*4882a593Smuzhiyun /* The CPU clock registers have Exynos5433-compatible layout */ 62*4882a593Smuzhiyun #define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 66*4882a593Smuzhiyun unsigned int lookup_id, const char *name, 67*4882a593Smuzhiyun const struct clk_hw *parent, const struct clk_hw *alt_parent, 68*4882a593Smuzhiyun unsigned long offset, 69*4882a593Smuzhiyun const struct exynos_cpuclk_cfg_data *cfg, 70*4882a593Smuzhiyun unsigned long num_cfgs, unsigned long flags); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __SAMSUNG_CLK_CPU_H */ 73