1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014 MundoReader S.L.
4*4882a593Smuzhiyun * Author: Heiko Stuebner <heiko@sntech.de>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/slab.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/reset-controller.h>
10*4882a593Smuzhiyun #include <linux/spinlock.h>
11*4882a593Smuzhiyun #include "clk.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct rockchip_softrst {
14*4882a593Smuzhiyun struct reset_controller_dev rcdev;
15*4882a593Smuzhiyun void __iomem *reg_base;
16*4882a593Smuzhiyun int num_regs;
17*4882a593Smuzhiyun int num_per_reg;
18*4882a593Smuzhiyun u8 flags;
19*4882a593Smuzhiyun spinlock_t lock;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
rockchip_softrst_assert(struct reset_controller_dev * rcdev,unsigned long id)22*4882a593Smuzhiyun static int rockchip_softrst_assert(struct reset_controller_dev *rcdev,
23*4882a593Smuzhiyun unsigned long id)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct rockchip_softrst *softrst = container_of(rcdev,
26*4882a593Smuzhiyun struct rockchip_softrst,
27*4882a593Smuzhiyun rcdev);
28*4882a593Smuzhiyun int bank = id / softrst->num_per_reg;
29*4882a593Smuzhiyun int offset = id % softrst->num_per_reg;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
32*4882a593Smuzhiyun writel(BIT(offset) | (BIT(offset) << 16),
33*4882a593Smuzhiyun softrst->reg_base + (bank * 4));
34*4882a593Smuzhiyun } else {
35*4882a593Smuzhiyun unsigned long flags;
36*4882a593Smuzhiyun u32 reg;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun spin_lock_irqsave(&softrst->lock, flags);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun reg = readl(softrst->reg_base + (bank * 4));
41*4882a593Smuzhiyun writel(reg | BIT(offset), softrst->reg_base + (bank * 4));
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun spin_unlock_irqrestore(&softrst->lock, flags);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
rockchip_softrst_deassert(struct reset_controller_dev * rcdev,unsigned long id)49*4882a593Smuzhiyun static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev,
50*4882a593Smuzhiyun unsigned long id)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct rockchip_softrst *softrst = container_of(rcdev,
53*4882a593Smuzhiyun struct rockchip_softrst,
54*4882a593Smuzhiyun rcdev);
55*4882a593Smuzhiyun int bank = id / softrst->num_per_reg;
56*4882a593Smuzhiyun int offset = id % softrst->num_per_reg;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
59*4882a593Smuzhiyun writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));
60*4882a593Smuzhiyun } else {
61*4882a593Smuzhiyun unsigned long flags;
62*4882a593Smuzhiyun u32 reg;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun spin_lock_irqsave(&softrst->lock, flags);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun reg = readl(softrst->reg_base + (bank * 4));
67*4882a593Smuzhiyun writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4));
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun spin_unlock_irqrestore(&softrst->lock, flags);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static const struct reset_control_ops rockchip_softrst_ops = {
76*4882a593Smuzhiyun .assert = rockchip_softrst_assert,
77*4882a593Smuzhiyun .deassert = rockchip_softrst_deassert,
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
rockchip_register_softrst(struct device_node * np,unsigned int num_regs,void __iomem * base,u8 flags)80*4882a593Smuzhiyun void rockchip_register_softrst(struct device_node *np,
81*4882a593Smuzhiyun unsigned int num_regs,
82*4882a593Smuzhiyun void __iomem *base, u8 flags)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct rockchip_softrst *softrst;
85*4882a593Smuzhiyun int ret;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun softrst = kzalloc(sizeof(*softrst), GFP_KERNEL);
88*4882a593Smuzhiyun if (!softrst)
89*4882a593Smuzhiyun return;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun spin_lock_init(&softrst->lock);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun softrst->reg_base = base;
94*4882a593Smuzhiyun softrst->flags = flags;
95*4882a593Smuzhiyun softrst->num_regs = num_regs;
96*4882a593Smuzhiyun softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16
97*4882a593Smuzhiyun : 32;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun softrst->rcdev.owner = THIS_MODULE;
100*4882a593Smuzhiyun softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg;
101*4882a593Smuzhiyun softrst->rcdev.ops = &rockchip_softrst_ops;
102*4882a593Smuzhiyun softrst->rcdev.of_node = np;
103*4882a593Smuzhiyun ret = reset_controller_register(&softrst->rcdev);
104*4882a593Smuzhiyun if (ret) {
105*4882a593Smuzhiyun pr_err("%s: could not register reset controller, %d\n",
106*4882a593Smuzhiyun __func__, ret);
107*4882a593Smuzhiyun kfree(softrst);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rockchip_register_softrst);
111