1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/of_address.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/pm_runtime.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static DEFINE_SPINLOCK(clk_out_lock);
14*4882a593Smuzhiyun
rockchip_clk_out_probe(struct platform_device * pdev)15*4882a593Smuzhiyun static int rockchip_clk_out_probe(struct platform_device *pdev)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun struct device *dev = &pdev->dev;
18*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
19*4882a593Smuzhiyun struct clk_hw *hw;
20*4882a593Smuzhiyun struct resource *res;
21*4882a593Smuzhiyun const char *clk_name = node->name;
22*4882a593Smuzhiyun const char *parent_name;
23*4882a593Smuzhiyun void __iomem *reg;
24*4882a593Smuzhiyun u32 shift = 0;
25*4882a593Smuzhiyun u8 clk_gate_flags = CLK_GATE_HIWORD_MASK;
26*4882a593Smuzhiyun int ret;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun ret = device_property_read_string(dev, "clock-output-names", &clk_name);
29*4882a593Smuzhiyun if (ret)
30*4882a593Smuzhiyun return ret;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun ret = device_property_read_u32(dev, "rockchip,bit-shift", &shift);
33*4882a593Smuzhiyun if (ret)
34*4882a593Smuzhiyun return ret;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (device_property_read_bool(dev, "rockchip,bit-set-to-disable"))
37*4882a593Smuzhiyun clk_gate_flags |= CLK_GATE_SET_TO_DISABLE;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun ret = of_clk_parent_fill(node, &parent_name, 1);
40*4882a593Smuzhiyun if (ret != 1)
41*4882a593Smuzhiyun return -EINVAL;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
44*4882a593Smuzhiyun if (!res)
45*4882a593Smuzhiyun return -ENOMEM;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun reg = devm_ioremap(dev, res->start, resource_size(res));
48*4882a593Smuzhiyun if (!reg)
49*4882a593Smuzhiyun return -ENOMEM;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun pm_runtime_enable(dev);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun hw = clk_hw_register_gate(dev, clk_name, parent_name, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
54*4882a593Smuzhiyun reg, shift, clk_gate_flags, &clk_out_lock);
55*4882a593Smuzhiyun if (IS_ERR(hw)) {
56*4882a593Smuzhiyun ret = -EINVAL;
57*4882a593Smuzhiyun goto err_disable_pm_runtime;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return 0;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun err_disable_pm_runtime:
65*4882a593Smuzhiyun pm_runtime_disable(dev);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return ret;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
rockchip_clk_out_remove(struct platform_device * pdev)70*4882a593Smuzhiyun static int rockchip_clk_out_remove(struct platform_device *pdev)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun of_clk_del_provider(node);
75*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static const struct of_device_id rockchip_clk_out_match[] = {
81*4882a593Smuzhiyun { .compatible = "rockchip,clk-out", },
82*4882a593Smuzhiyun {},
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static struct platform_driver rockchip_clk_out_driver = {
86*4882a593Smuzhiyun .driver = {
87*4882a593Smuzhiyun .name = "rockchip-clk-out",
88*4882a593Smuzhiyun .of_match_table = rockchip_clk_out_match,
89*4882a593Smuzhiyun },
90*4882a593Smuzhiyun .probe = rockchip_clk_out_probe,
91*4882a593Smuzhiyun .remove = rockchip_clk_out_remove,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun module_platform_driver(rockchip_clk_out_driver);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun MODULE_DESCRIPTION("Rockchip Clock Input-Output-Switch");
97*4882a593Smuzhiyun MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
98*4882a593Smuzhiyun MODULE_LICENSE("GPL");
99*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rockchip_clk_out_match);
100