1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun# common clock support for ROCKCHIP SoC family. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyunconfig COMMON_CLK_ROCKCHIP 5*4882a593Smuzhiyun tristate "Rockchip clock controller common support" 6*4882a593Smuzhiyun depends on ARCH_ROCKCHIP 7*4882a593Smuzhiyun default ARCH_ROCKCHIP 8*4882a593Smuzhiyun help 9*4882a593Smuzhiyun Say y here to enable common clock controller for Rockchip platforms. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunif COMMON_CLK_ROCKCHIP 12*4882a593Smuzhiyunconfig CLK_PX30 13*4882a593Smuzhiyun tristate "Rockchip PX30 clock controller support" 14*4882a593Smuzhiyun depends on CPU_PX30 || COMPILE_TEST 15*4882a593Smuzhiyun default y 16*4882a593Smuzhiyun help 17*4882a593Smuzhiyun Build the driver for PX30 Clock Driver. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunconfig CLK_RV1106 20*4882a593Smuzhiyun tristate "Rockchip RV1106 clock controller support" 21*4882a593Smuzhiyun depends on CPU_RV1106 || COMPILE_TEST 22*4882a593Smuzhiyun default y 23*4882a593Smuzhiyun help 24*4882a593Smuzhiyun Build the driver for RV1106 Clock Driver. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunconfig CLK_RV1108 27*4882a593Smuzhiyun tristate "Rockchip RV1108 clock controller support" 28*4882a593Smuzhiyun depends on CPU_RV1108 || COMPILE_TEST 29*4882a593Smuzhiyun default y 30*4882a593Smuzhiyun help 31*4882a593Smuzhiyun Build the driver for RV1108 Clock Driver. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyunconfig CLK_RV1126 34*4882a593Smuzhiyun tristate "Rockchip RV1126 clock controller support" 35*4882a593Smuzhiyun depends on CPU_RV1126 || COMPILE_TEST 36*4882a593Smuzhiyun default y 37*4882a593Smuzhiyun help 38*4882a593Smuzhiyun Build the driver for RV1126 Clock Driver. 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunconfig CLK_RK1808 41*4882a593Smuzhiyun tristate "Rockchip RK1808 clock controller support" 42*4882a593Smuzhiyun depends on CPU_RK1808 || COMPILE_TEST 43*4882a593Smuzhiyun default y 44*4882a593Smuzhiyun help 45*4882a593Smuzhiyun Build the driver for RK1808 Clock Driver. 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunconfig CLK_RK3036 48*4882a593Smuzhiyun tristate "Rockchip RK3036 clock controller support" 49*4882a593Smuzhiyun depends on CPU_RK3036 || COMPILE_TEST 50*4882a593Smuzhiyun default y 51*4882a593Smuzhiyun help 52*4882a593Smuzhiyun Build the driver for RK3036 Clock Driver. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunconfig CLK_RK312X 55*4882a593Smuzhiyun tristate "Rockchip RK312x clock controller support" 56*4882a593Smuzhiyun depends on CPU_RK312X || COMPILE_TEST 57*4882a593Smuzhiyun default y 58*4882a593Smuzhiyun help 59*4882a593Smuzhiyun Build the driver for RK312x Clock Driver. 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunconfig CLK_RK3188 62*4882a593Smuzhiyun tristate "Rockchip RK3188 clock controller support" 63*4882a593Smuzhiyun depends on CPU_RK3188 || COMPILE_TEST 64*4882a593Smuzhiyun default y 65*4882a593Smuzhiyun help 66*4882a593Smuzhiyun Build the driver for RK3188 Clock Driver. 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunconfig CLK_RK322X 69*4882a593Smuzhiyun tristate "Rockchip RK322x clock controller support" 70*4882a593Smuzhiyun depends on CPU_RK322X || COMPILE_TEST 71*4882a593Smuzhiyun default y 72*4882a593Smuzhiyun help 73*4882a593Smuzhiyun Build the driver for RK322x Clock Driver. 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunconfig CLK_RK3288 76*4882a593Smuzhiyun tristate "Rockchip RK3288 clock controller support" 77*4882a593Smuzhiyun depends on CPU_RK3288 || COMPILE_TEST 78*4882a593Smuzhiyun default y 79*4882a593Smuzhiyun help 80*4882a593Smuzhiyun Build the driver for RK3288 Clock Driver. 81*4882a593Smuzhiyun 82*4882a593Smuzhiyunconfig CLK_RK3308 83*4882a593Smuzhiyun tristate "Rockchip RK3308 clock controller support" 84*4882a593Smuzhiyun depends on CPU_RK3308 || COMPILE_TEST 85*4882a593Smuzhiyun default y 86*4882a593Smuzhiyun help 87*4882a593Smuzhiyun Build the driver for RK3308 Clock Driver. 88*4882a593Smuzhiyun 89*4882a593Smuzhiyunconfig CLK_RK3328 90*4882a593Smuzhiyun tristate "Rockchip RK3328 clock controller support" 91*4882a593Smuzhiyun depends on CPU_RK3328 || COMPILE_TEST 92*4882a593Smuzhiyun default y 93*4882a593Smuzhiyun help 94*4882a593Smuzhiyun Build the driver for RK3328 Clock Driver. 95*4882a593Smuzhiyun 96*4882a593Smuzhiyunconfig CLK_RK3368 97*4882a593Smuzhiyun tristate "Rockchip RK3368 clock controller support" 98*4882a593Smuzhiyun depends on CPU_RK3368 || COMPILE_TEST 99*4882a593Smuzhiyun default y 100*4882a593Smuzhiyun help 101*4882a593Smuzhiyun Build the driver for RK3368 Clock Driver. 102*4882a593Smuzhiyun 103*4882a593Smuzhiyunconfig CLK_RK3399 104*4882a593Smuzhiyun tristate "Rockchip RK3399 clock controller support" 105*4882a593Smuzhiyun depends on CPU_RK3399 || COMPILE_TEST 106*4882a593Smuzhiyun default y 107*4882a593Smuzhiyun help 108*4882a593Smuzhiyun Build the driver for RK3399 Clock Driver. 109*4882a593Smuzhiyun 110*4882a593Smuzhiyunconfig CLK_RK3528 111*4882a593Smuzhiyun tristate "Rockchip RK3528 clock controller support" 112*4882a593Smuzhiyun depends on CPU_RK3528 || COMPILE_TEST 113*4882a593Smuzhiyun default y 114*4882a593Smuzhiyun help 115*4882a593Smuzhiyun Build the driver for RK3528 Clock Driver. 116*4882a593Smuzhiyun 117*4882a593Smuzhiyunconfig CLK_RK3562 118*4882a593Smuzhiyun tristate "Rockchip RK3562 clock controller support" 119*4882a593Smuzhiyun depends on CPU_RK3562 || COMPILE_TEST 120*4882a593Smuzhiyun default y 121*4882a593Smuzhiyun help 122*4882a593Smuzhiyun Build the driver for RK3562 Clock Driver. 123*4882a593Smuzhiyun 124*4882a593Smuzhiyunconfig CLK_RK3568 125*4882a593Smuzhiyun tristate "Rockchip RK3568 clock controller support" 126*4882a593Smuzhiyun depends on CPU_RK3568 || COMPILE_TEST 127*4882a593Smuzhiyun default y 128*4882a593Smuzhiyun help 129*4882a593Smuzhiyun Build the driver for RK3568 Clock Driver. 130*4882a593Smuzhiyun 131*4882a593Smuzhiyunconfig CLK_RK3588 132*4882a593Smuzhiyun tristate "Rockchip RK3588 clock controller support" 133*4882a593Smuzhiyun depends on CPU_RK3588 || COMPILE_TEST 134*4882a593Smuzhiyun default y 135*4882a593Smuzhiyun help 136*4882a593Smuzhiyun Build the driver for RK3588 Clock Driver. 137*4882a593Smuzhiyun 138*4882a593Smuzhiyunconfig ROCKCHIP_CLK_COMPENSATION 139*4882a593Smuzhiyun bool "Rockchip Clk Compensation" 140*4882a593Smuzhiyun help 141*4882a593Smuzhiyun Say y here to enable clk compensation(+/- 1000 ppm). 142*4882a593Smuzhiyun 143*4882a593Smuzhiyunconfig ROCKCHIP_CLK_LINK 144*4882a593Smuzhiyun tristate "Rockchip clock link support" 145*4882a593Smuzhiyun default CLK_RK3562 || CLK_RK3588 146*4882a593Smuzhiyun help 147*4882a593Smuzhiyun Say y here to enable clock link for Rockchip. 148*4882a593Smuzhiyun 149*4882a593Smuzhiyunconfig ROCKCHIP_CLK_BOOST 150*4882a593Smuzhiyun bool "Rockchip Clk Boost" 151*4882a593Smuzhiyun default y if CPU_PX30 152*4882a593Smuzhiyun help 153*4882a593Smuzhiyun Say y here to enable clk boost. 154*4882a593Smuzhiyun 155*4882a593Smuzhiyunconfig ROCKCHIP_CLK_INV 156*4882a593Smuzhiyun bool "Rockchip Clk Inverter" 157*4882a593Smuzhiyun default y if !CPU_RV1126 && !CPU_RV1106 158*4882a593Smuzhiyun help 159*4882a593Smuzhiyun Say y here to enable clk Inverter. 160*4882a593Smuzhiyun 161*4882a593Smuzhiyunconfig ROCKCHIP_CLK_OUT 162*4882a593Smuzhiyun tristate "Rockchip Clk Out / Input Switch" 163*4882a593Smuzhiyun default y if !ROCKCHIP_MINI_KERNEL 164*4882a593Smuzhiyun help 165*4882a593Smuzhiyun Say y here to enable clk out / input switch. 166*4882a593Smuzhiyun 167*4882a593Smuzhiyunconfig ROCKCHIP_CLK_PVTM 168*4882a593Smuzhiyun bool "Rockchip Clk Pvtm" 169*4882a593Smuzhiyun default y if !CPU_RV1126 && !CPU_RV1106 170*4882a593Smuzhiyun help 171*4882a593Smuzhiyun Say y here to enable clk pvtm. 172*4882a593Smuzhiyun 173*4882a593Smuzhiyunconfig ROCKCHIP_DDRCLK 174*4882a593Smuzhiyun bool 175*4882a593Smuzhiyun 176*4882a593Smuzhiyunconfig ROCKCHIP_DDRCLK_SIP 177*4882a593Smuzhiyun bool "Rockchip DDR Clk SIP" 178*4882a593Smuzhiyun default y if CPU_RK3399 179*4882a593Smuzhiyun select ROCKCHIP_DDRCLK 180*4882a593Smuzhiyun help 181*4882a593Smuzhiyun Say y here to enable ddr clk sip. 182*4882a593Smuzhiyun 183*4882a593Smuzhiyunconfig ROCKCHIP_DDRCLK_SIP_V2 184*4882a593Smuzhiyun bool "Rockchip DDR Clk SIP V2" 185*4882a593Smuzhiyun default y if CPU_PX30 || CPU_RK1808 || CPU_RK312X || CPU_RK322X || \ 186*4882a593Smuzhiyun CPU_RK3288 || CPU_RK3308 || CPU_RK3328 || CPU_RV1126 187*4882a593Smuzhiyun select ROCKCHIP_DDRCLK 188*4882a593Smuzhiyun help 189*4882a593Smuzhiyun Say y here to enable ddr clk sip v2. 190*4882a593Smuzhiyun 191*4882a593Smuzhiyunconfig ROCKCHIP_PLL_RK3066 192*4882a593Smuzhiyun bool "Rockchip PLL Type RK3066" 193*4882a593Smuzhiyun default y if CPU_RK30XX || CPU_RK3188 || \ 194*4882a593Smuzhiyun CPU_RK3288 || CPU_RK3368 195*4882a593Smuzhiyun help 196*4882a593Smuzhiyun Say y here to enable pll type is rk3066. 197*4882a593Smuzhiyun 198*4882a593Smuzhiyunconfig ROCKCHIP_PLL_RK3399 199*4882a593Smuzhiyun bool "Rockchip PLL Type RK3399" 200*4882a593Smuzhiyun default y if CPU_RK3399 || CPU_RV1108 201*4882a593Smuzhiyun help 202*4882a593Smuzhiyun Say y here to enable pll type is rk3399. 203*4882a593Smuzhiyun 204*4882a593Smuzhiyunconfig ROCKCHIP_PLL_RK3588 205*4882a593Smuzhiyun bool "Rockchip PLL Type RK3588" 206*4882a593Smuzhiyun default y if CPU_RK3588 207*4882a593Smuzhiyun help 208*4882a593Smuzhiyun Say y here to enable pll type is rk3588. 209*4882a593Smuzhiyun 210*4882a593Smuzhiyunsource "drivers/clk/rockchip/regmap/Kconfig" 211*4882a593Smuzhiyun 212*4882a593Smuzhiyunendif 213