1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * R-Car Gen2 Clock Pulse Generator 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Cogent Embedded Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__ 9*4882a593Smuzhiyun #define __CLK_RENESAS_RCAR_GEN2_CPG_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun enum rcar_gen2_clk_types { 12*4882a593Smuzhiyun CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM, 13*4882a593Smuzhiyun CLK_TYPE_GEN2_PLL0, 14*4882a593Smuzhiyun CLK_TYPE_GEN2_PLL1, 15*4882a593Smuzhiyun CLK_TYPE_GEN2_PLL3, 16*4882a593Smuzhiyun CLK_TYPE_GEN2_Z, 17*4882a593Smuzhiyun CLK_TYPE_GEN2_LB, 18*4882a593Smuzhiyun CLK_TYPE_GEN2_ADSP, 19*4882a593Smuzhiyun CLK_TYPE_GEN2_SDH, 20*4882a593Smuzhiyun CLK_TYPE_GEN2_SD0, 21*4882a593Smuzhiyun CLK_TYPE_GEN2_SD1, 22*4882a593Smuzhiyun CLK_TYPE_GEN2_QSPI, 23*4882a593Smuzhiyun CLK_TYPE_GEN2_RCAN, 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct rcar_gen2_cpg_pll_config { 27*4882a593Smuzhiyun u8 extal_div; 28*4882a593Smuzhiyun u8 pll1_mult; 29*4882a593Smuzhiyun u8 pll3_mult; 30*4882a593Smuzhiyun u8 pll0_mult; /* leave as zero if PLL0CR exists */ 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct clk *rcar_gen2_cpg_clk_register(struct device *dev, 34*4882a593Smuzhiyun const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 35*4882a593Smuzhiyun struct clk **clks, void __iomem *base, 36*4882a593Smuzhiyun struct raw_notifier_head *notifiers); 37*4882a593Smuzhiyun int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, 38*4882a593Smuzhiyun unsigned int pll0_div, u32 mode); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif 41