1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * RZ/A1 Core CPG Clocks
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Ideas On Board SPRL
6*4882a593Smuzhiyun * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/clk/renesas.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_address.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct rz_cpg {
19*4882a593Smuzhiyun struct clk_onecell_data data;
20*4882a593Smuzhiyun void __iomem *reg;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define CPG_FRQCR 0x10
24*4882a593Smuzhiyun #define CPG_FRQCR2 0x14
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define PPR0 0xFCFE3200
27*4882a593Smuzhiyun #define PIBC0 0xFCFE7000
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
32*4882a593Smuzhiyun * Initialization
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun
rz_cpg_read_mode_pins(void)35*4882a593Smuzhiyun static u16 __init rz_cpg_read_mode_pins(void)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun void __iomem *ppr0, *pibc0;
38*4882a593Smuzhiyun u16 modes;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun ppr0 = ioremap(PPR0, 2);
41*4882a593Smuzhiyun pibc0 = ioremap(PIBC0, 2);
42*4882a593Smuzhiyun BUG_ON(!ppr0 || !pibc0);
43*4882a593Smuzhiyun iowrite16(4, pibc0); /* enable input buffer */
44*4882a593Smuzhiyun modes = ioread16(ppr0);
45*4882a593Smuzhiyun iounmap(ppr0);
46*4882a593Smuzhiyun iounmap(pibc0);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return modes;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static struct clk * __init
rz_cpg_register_clock(struct device_node * np,struct rz_cpg * cpg,const char * name)52*4882a593Smuzhiyun rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun u32 val;
55*4882a593Smuzhiyun unsigned mult;
56*4882a593Smuzhiyun static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (strcmp(name, "pll") == 0) {
59*4882a593Smuzhiyun unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
60*4882a593Smuzhiyun const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun mult = cpg_mode ? (32 / 4) : 30;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
68*4882a593Smuzhiyun if (!cpg->reg)
69*4882a593Smuzhiyun return ERR_PTR(-ENXIO);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
72*4882a593Smuzhiyun * and the constraint that always g <= i. To get the rz platform started,
73*4882a593Smuzhiyun * let them run at fixed current speed and implement the details later.
74*4882a593Smuzhiyun */
75*4882a593Smuzhiyun if (strcmp(name, "i") == 0)
76*4882a593Smuzhiyun val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
77*4882a593Smuzhiyun else if (strcmp(name, "g") == 0)
78*4882a593Smuzhiyun val = readl(cpg->reg + CPG_FRQCR2) & 3;
79*4882a593Smuzhiyun else
80*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun mult = frqcr_tab[val];
83*4882a593Smuzhiyun return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
rz_cpg_clocks_init(struct device_node * np)86*4882a593Smuzhiyun static void __init rz_cpg_clocks_init(struct device_node *np)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct rz_cpg *cpg;
89*4882a593Smuzhiyun struct clk **clks;
90*4882a593Smuzhiyun unsigned i;
91*4882a593Smuzhiyun int num_clks;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun num_clks = of_property_count_strings(np, "clock-output-names");
94*4882a593Smuzhiyun if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
95*4882a593Smuzhiyun return;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
98*4882a593Smuzhiyun clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
99*4882a593Smuzhiyun BUG_ON(!cpg || !clks);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun cpg->data.clks = clks;
102*4882a593Smuzhiyun cpg->data.clk_num = num_clks;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun cpg->reg = of_iomap(np, 0);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun for (i = 0; i < num_clks; ++i) {
107*4882a593Smuzhiyun const char *name;
108*4882a593Smuzhiyun struct clk *clk;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun of_property_read_string_index(np, "clock-output-names", i, &name);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun clk = rz_cpg_register_clock(np, cpg, name);
113*4882a593Smuzhiyun if (IS_ERR(clk))
114*4882a593Smuzhiyun pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
115*4882a593Smuzhiyun __func__, np, name, PTR_ERR(clk));
116*4882a593Smuzhiyun else
117*4882a593Smuzhiyun cpg->data.clks[i] = clk;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun cpg_mstp_add_clk_domain(np);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
125