1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * EMMA Mobile EV2 common clock framework support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
6*4882a593Smuzhiyun * Copyright (C) 2012 Magnus Damm
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/clkdev.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* EMEV2 SMU registers */
15*4882a593Smuzhiyun #define USIAU0_RSTCTRL 0x094
16*4882a593Smuzhiyun #define USIBU1_RSTCTRL 0x0ac
17*4882a593Smuzhiyun #define USIBU2_RSTCTRL 0x0b0
18*4882a593Smuzhiyun #define USIBU3_RSTCTRL 0x0b4
19*4882a593Smuzhiyun #define IIC0_RSTCTRL 0x0dc
20*4882a593Smuzhiyun #define IIC1_RSTCTRL 0x0e0
21*4882a593Smuzhiyun #define STI_RSTCTRL 0x124
22*4882a593Smuzhiyun #define STI_CLKSEL 0x688
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static DEFINE_SPINLOCK(lock);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* not pretty, but hey */
27*4882a593Smuzhiyun static void __iomem *smu_base;
28*4882a593Smuzhiyun
emev2_smu_write(unsigned long value,int offs)29*4882a593Smuzhiyun static void __init emev2_smu_write(unsigned long value, int offs)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun BUG_ON(!smu_base || (offs >= PAGE_SIZE));
32*4882a593Smuzhiyun writel_relaxed(value, smu_base + offs);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static const struct of_device_id smu_id[] __initconst = {
36*4882a593Smuzhiyun { .compatible = "renesas,emev2-smu", },
37*4882a593Smuzhiyun {},
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
emev2_smu_init(void)40*4882a593Smuzhiyun static void __init emev2_smu_init(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct device_node *np;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun np = of_find_matching_node(NULL, smu_id);
45*4882a593Smuzhiyun BUG_ON(!np);
46*4882a593Smuzhiyun smu_base = of_iomap(np, 0);
47*4882a593Smuzhiyun BUG_ON(!smu_base);
48*4882a593Smuzhiyun of_node_put(np);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* setup STI timer to run on 32.768 kHz and deassert reset */
51*4882a593Smuzhiyun emev2_smu_write(0, STI_CLKSEL);
52*4882a593Smuzhiyun emev2_smu_write(1, STI_RSTCTRL);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* deassert reset for UART0->UART3 */
55*4882a593Smuzhiyun emev2_smu_write(2, USIAU0_RSTCTRL);
56*4882a593Smuzhiyun emev2_smu_write(2, USIBU1_RSTCTRL);
57*4882a593Smuzhiyun emev2_smu_write(2, USIBU2_RSTCTRL);
58*4882a593Smuzhiyun emev2_smu_write(2, USIBU3_RSTCTRL);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* deassert reset for IIC0->IIC1 */
61*4882a593Smuzhiyun emev2_smu_write(1, IIC0_RSTCTRL);
62*4882a593Smuzhiyun emev2_smu_write(1, IIC1_RSTCTRL);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
emev2_smu_clkdiv_init(struct device_node * np)65*4882a593Smuzhiyun static void __init emev2_smu_clkdiv_init(struct device_node *np)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun u32 reg[2];
68*4882a593Smuzhiyun struct clk *clk;
69*4882a593Smuzhiyun const char *parent_name = of_clk_get_parent_name(np, 0);
70*4882a593Smuzhiyun if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
71*4882a593Smuzhiyun return;
72*4882a593Smuzhiyun if (!smu_base)
73*4882a593Smuzhiyun emev2_smu_init();
74*4882a593Smuzhiyun clk = clk_register_divider(NULL, np->name, parent_name, 0,
75*4882a593Smuzhiyun smu_base + reg[0], reg[1], 8, 0, &lock);
76*4882a593Smuzhiyun of_clk_add_provider(np, of_clk_src_simple_get, clk);
77*4882a593Smuzhiyun clk_register_clkdev(clk, np->full_name, NULL);
78*4882a593Smuzhiyun pr_debug("## %s %pOFn %p\n", __func__, np, clk);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
81*4882a593Smuzhiyun emev2_smu_clkdiv_init);
82*4882a593Smuzhiyun
emev2_smu_gclk_init(struct device_node * np)83*4882a593Smuzhiyun static void __init emev2_smu_gclk_init(struct device_node *np)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun u32 reg[2];
86*4882a593Smuzhiyun struct clk *clk;
87*4882a593Smuzhiyun const char *parent_name = of_clk_get_parent_name(np, 0);
88*4882a593Smuzhiyun if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
89*4882a593Smuzhiyun return;
90*4882a593Smuzhiyun if (!smu_base)
91*4882a593Smuzhiyun emev2_smu_init();
92*4882a593Smuzhiyun clk = clk_register_gate(NULL, np->name, parent_name, 0,
93*4882a593Smuzhiyun smu_base + reg[0], reg[1], 0, &lock);
94*4882a593Smuzhiyun of_clk_add_provider(np, of_clk_src_simple_get, clk);
95*4882a593Smuzhiyun clk_register_clkdev(clk, np->full_name, NULL);
96*4882a593Smuzhiyun pr_debug("## %s %pOFn %p\n", __func__, np, clk);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
99