1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunconfig CLK_RENESAS 4*4882a593Smuzhiyun bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS 5*4882a593Smuzhiyun default y if ARCH_RENESAS 6*4882a593Smuzhiyun select CLK_EMEV2 if ARCH_EMEV2 7*4882a593Smuzhiyun select CLK_RZA1 if ARCH_R7S72100 8*4882a593Smuzhiyun select CLK_R7S9210 if ARCH_R7S9210 9*4882a593Smuzhiyun select CLK_R8A73A4 if ARCH_R8A73A4 10*4882a593Smuzhiyun select CLK_R8A7740 if ARCH_R8A7740 11*4882a593Smuzhiyun select CLK_R8A7742 if ARCH_R8A7742 12*4882a593Smuzhiyun select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744 13*4882a593Smuzhiyun select CLK_R8A7745 if ARCH_R8A7745 14*4882a593Smuzhiyun select CLK_R8A77470 if ARCH_R8A77470 15*4882a593Smuzhiyun select CLK_R8A774A1 if ARCH_R8A774A1 16*4882a593Smuzhiyun select CLK_R8A774B1 if ARCH_R8A774B1 17*4882a593Smuzhiyun select CLK_R8A774C0 if ARCH_R8A774C0 18*4882a593Smuzhiyun select CLK_R8A774E1 if ARCH_R8A774E1 19*4882a593Smuzhiyun select CLK_R8A7778 if ARCH_R8A7778 20*4882a593Smuzhiyun select CLK_R8A7779 if ARCH_R8A7779 21*4882a593Smuzhiyun select CLK_R8A7790 if ARCH_R8A7790 22*4882a593Smuzhiyun select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 23*4882a593Smuzhiyun select CLK_R8A7792 if ARCH_R8A7792 24*4882a593Smuzhiyun select CLK_R8A7794 if ARCH_R8A7794 25*4882a593Smuzhiyun select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951 26*4882a593Smuzhiyun select CLK_R8A77960 if ARCH_R8A77960 27*4882a593Smuzhiyun select CLK_R8A77961 if ARCH_R8A77961 28*4882a593Smuzhiyun select CLK_R8A77965 if ARCH_R8A77965 29*4882a593Smuzhiyun select CLK_R8A77970 if ARCH_R8A77970 30*4882a593Smuzhiyun select CLK_R8A77980 if ARCH_R8A77980 31*4882a593Smuzhiyun select CLK_R8A77990 if ARCH_R8A77990 32*4882a593Smuzhiyun select CLK_R8A77995 if ARCH_R8A77995 33*4882a593Smuzhiyun select CLK_R8A779A0 if ARCH_R8A779A0 34*4882a593Smuzhiyun select CLK_R9A06G032 if ARCH_R9A06G032 35*4882a593Smuzhiyun select CLK_SH73A0 if ARCH_SH73A0 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunif CLK_RENESAS 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun# SoC 40*4882a593Smuzhiyunconfig CLK_EMEV2 41*4882a593Smuzhiyun bool "Emma Mobile EV2 clock support" if COMPILE_TEST 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunconfig CLK_RZA1 44*4882a593Smuzhiyun bool "RZ/A1H clock support" if COMPILE_TEST 45*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSTP 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunconfig CLK_R7S9210 48*4882a593Smuzhiyun bool "RZ/A2 clock support" if COMPILE_TEST 49*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSSR 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunconfig CLK_R8A73A4 52*4882a593Smuzhiyun bool "R-Mobile APE6 clock support" if COMPILE_TEST 53*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSTP 54*4882a593Smuzhiyun select CLK_RENESAS_DIV6 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunconfig CLK_R8A7740 57*4882a593Smuzhiyun bool "R-Mobile A1 clock support" if COMPILE_TEST 58*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSTP 59*4882a593Smuzhiyun select CLK_RENESAS_DIV6 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunconfig CLK_R8A7742 62*4882a593Smuzhiyun bool "RZ/G1H clock support" if COMPILE_TEST 63*4882a593Smuzhiyun select CLK_RCAR_GEN2_CPG 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunconfig CLK_R8A7743 66*4882a593Smuzhiyun bool "RZ/G1M clock support" if COMPILE_TEST 67*4882a593Smuzhiyun select CLK_RCAR_GEN2_CPG 68*4882a593Smuzhiyun 69*4882a593Smuzhiyunconfig CLK_R8A7745 70*4882a593Smuzhiyun bool "RZ/G1E clock support" if COMPILE_TEST 71*4882a593Smuzhiyun select CLK_RCAR_GEN2_CPG 72*4882a593Smuzhiyun 73*4882a593Smuzhiyunconfig CLK_R8A77470 74*4882a593Smuzhiyun bool "RZ/G1C clock support" if COMPILE_TEST 75*4882a593Smuzhiyun select CLK_RCAR_GEN2_CPG 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunconfig CLK_R8A774A1 78*4882a593Smuzhiyun bool "RZ/G2M clock support" if COMPILE_TEST 79*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 80*4882a593Smuzhiyun 81*4882a593Smuzhiyunconfig CLK_R8A774B1 82*4882a593Smuzhiyun bool "RZ/G2N clock support" if COMPILE_TEST 83*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 84*4882a593Smuzhiyun 85*4882a593Smuzhiyunconfig CLK_R8A774C0 86*4882a593Smuzhiyun bool "RZ/G2E clock support" if COMPILE_TEST 87*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 88*4882a593Smuzhiyun 89*4882a593Smuzhiyunconfig CLK_R8A774E1 90*4882a593Smuzhiyun bool "RZ/G2H clock support" if COMPILE_TEST 91*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 92*4882a593Smuzhiyun 93*4882a593Smuzhiyunconfig CLK_R8A7778 94*4882a593Smuzhiyun bool "R-Car M1A clock support" if COMPILE_TEST 95*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSTP 96*4882a593Smuzhiyun 97*4882a593Smuzhiyunconfig CLK_R8A7779 98*4882a593Smuzhiyun bool "R-Car H1 clock support" if COMPILE_TEST 99*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSTP 100*4882a593Smuzhiyun 101*4882a593Smuzhiyunconfig CLK_R8A7790 102*4882a593Smuzhiyun bool "R-Car H2 clock support" if COMPILE_TEST 103*4882a593Smuzhiyun select CLK_RCAR_GEN2_CPG 104*4882a593Smuzhiyun 105*4882a593Smuzhiyunconfig CLK_R8A7791 106*4882a593Smuzhiyun bool "R-Car M2-W/N clock support" if COMPILE_TEST 107*4882a593Smuzhiyun select CLK_RCAR_GEN2_CPG 108*4882a593Smuzhiyun 109*4882a593Smuzhiyunconfig CLK_R8A7792 110*4882a593Smuzhiyun bool "R-Car V2H clock support" if COMPILE_TEST 111*4882a593Smuzhiyun select CLK_RCAR_GEN2_CPG 112*4882a593Smuzhiyun 113*4882a593Smuzhiyunconfig CLK_R8A7794 114*4882a593Smuzhiyun bool "R-Car E2 clock support" if COMPILE_TEST 115*4882a593Smuzhiyun select CLK_RCAR_GEN2_CPG 116*4882a593Smuzhiyun 117*4882a593Smuzhiyunconfig CLK_R8A7795 118*4882a593Smuzhiyun bool "R-Car H3 clock support" if COMPILE_TEST 119*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 120*4882a593Smuzhiyun 121*4882a593Smuzhiyunconfig CLK_R8A77960 122*4882a593Smuzhiyun bool "R-Car M3-W clock support" if COMPILE_TEST 123*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 124*4882a593Smuzhiyun 125*4882a593Smuzhiyunconfig CLK_R8A77961 126*4882a593Smuzhiyun bool "R-Car M3-W+ clock support" if COMPILE_TEST 127*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 128*4882a593Smuzhiyun 129*4882a593Smuzhiyunconfig CLK_R8A77965 130*4882a593Smuzhiyun bool "R-Car M3-N clock support" if COMPILE_TEST 131*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 132*4882a593Smuzhiyun 133*4882a593Smuzhiyunconfig CLK_R8A77970 134*4882a593Smuzhiyun bool "R-Car V3M clock support" if COMPILE_TEST 135*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 136*4882a593Smuzhiyun 137*4882a593Smuzhiyunconfig CLK_R8A77980 138*4882a593Smuzhiyun bool "R-Car V3H clock support" if COMPILE_TEST 139*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 140*4882a593Smuzhiyun 141*4882a593Smuzhiyunconfig CLK_R8A77990 142*4882a593Smuzhiyun bool "R-Car E3 clock support" if COMPILE_TEST 143*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 144*4882a593Smuzhiyun 145*4882a593Smuzhiyunconfig CLK_R8A77995 146*4882a593Smuzhiyun bool "R-Car D3 clock support" if COMPILE_TEST 147*4882a593Smuzhiyun select CLK_RCAR_GEN3_CPG 148*4882a593Smuzhiyun 149*4882a593Smuzhiyunconfig CLK_R8A779A0 150*4882a593Smuzhiyun bool "R-Car V3U clock support" if COMPILE_TEST 151*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSSR 152*4882a593Smuzhiyun 153*4882a593Smuzhiyunconfig CLK_R9A06G032 154*4882a593Smuzhiyun bool "Renesas R9A06G032 clock driver" 155*4882a593Smuzhiyun help 156*4882a593Smuzhiyun This is a driver for R9A06G032 clocks 157*4882a593Smuzhiyun 158*4882a593Smuzhiyunconfig CLK_SH73A0 159*4882a593Smuzhiyun bool "SH-Mobile AG5 clock support" if COMPILE_TEST 160*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSTP 161*4882a593Smuzhiyun select CLK_RENESAS_DIV6 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun# Family 165*4882a593Smuzhiyunconfig CLK_RCAR_GEN2_CPG 166*4882a593Smuzhiyun bool "R-Car Gen2 CPG clock support" if COMPILE_TEST 167*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSSR 168*4882a593Smuzhiyun 169*4882a593Smuzhiyunconfig CLK_RCAR_GEN3_CPG 170*4882a593Smuzhiyun bool "R-Car Gen3 and RZ/G2 CPG clock support" if COMPILE_TEST 171*4882a593Smuzhiyun select CLK_RENESAS_CPG_MSSR 172*4882a593Smuzhiyun 173*4882a593Smuzhiyunconfig CLK_RCAR_USB2_CLOCK_SEL 174*4882a593Smuzhiyun bool "Renesas R-Car USB2 clock selector support" 175*4882a593Smuzhiyun depends on ARCH_RENESAS || COMPILE_TEST 176*4882a593Smuzhiyun select RESET_CONTROLLER 177*4882a593Smuzhiyun help 178*4882a593Smuzhiyun This is a driver for R-Car USB2 clock selector 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun# Generic 181*4882a593Smuzhiyunconfig CLK_RENESAS_CPG_MSSR 182*4882a593Smuzhiyun bool "CPG/MSSR clock support" if COMPILE_TEST 183*4882a593Smuzhiyun select CLK_RENESAS_DIV6 184*4882a593Smuzhiyun 185*4882a593Smuzhiyunconfig CLK_RENESAS_CPG_MSTP 186*4882a593Smuzhiyun bool "MSTP clock support" if COMPILE_TEST 187*4882a593Smuzhiyun 188*4882a593Smuzhiyunconfig CLK_RENESAS_DIV6 189*4882a593Smuzhiyun bool "DIV6 clock support" if COMPILE_TEST 190*4882a593Smuzhiyun 191*4882a593Smuzhiyunendif # CLK_RENESAS 192