xref: /OK3568_Linux_fs/kernel/drivers/clk/qcom/mss-sc7180.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/platform_device.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/pm_clock.h>
10*4882a593Smuzhiyun #include <linux/pm_runtime.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,mss-sc7180.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include "clk-regmap.h"
16*4882a593Smuzhiyun #include "clk-branch.h"
17*4882a593Smuzhiyun #include "common.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun static struct clk_branch mss_axi_nav_clk = {
20*4882a593Smuzhiyun 	.halt_reg = 0x20bc,
21*4882a593Smuzhiyun 	.halt_check = BRANCH_HALT,
22*4882a593Smuzhiyun 	.clkr = {
23*4882a593Smuzhiyun 		.enable_reg = 0x20bc,
24*4882a593Smuzhiyun 		.enable_mask = BIT(0),
25*4882a593Smuzhiyun 		.hw.init = &(struct clk_init_data){
26*4882a593Smuzhiyun 			.name = "mss_axi_nav_clk",
27*4882a593Smuzhiyun 			.parent_data = &(const struct clk_parent_data){
28*4882a593Smuzhiyun 				.fw_name = "gcc_mss_nav_axi",
29*4882a593Smuzhiyun 			},
30*4882a593Smuzhiyun 			.num_parents = 1,
31*4882a593Smuzhiyun 			.ops = &clk_branch2_ops,
32*4882a593Smuzhiyun 		},
33*4882a593Smuzhiyun 	},
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun static struct clk_branch mss_axi_crypto_clk = {
37*4882a593Smuzhiyun 	.halt_reg = 0x20cc,
38*4882a593Smuzhiyun 	.halt_check = BRANCH_HALT,
39*4882a593Smuzhiyun 	.clkr = {
40*4882a593Smuzhiyun 		.enable_reg = 0x20cc,
41*4882a593Smuzhiyun 		.enable_mask = BIT(0),
42*4882a593Smuzhiyun 		.hw.init = &(struct clk_init_data){
43*4882a593Smuzhiyun 			.name = "mss_axi_crypto_clk",
44*4882a593Smuzhiyun 			.parent_data = &(const struct clk_parent_data){
45*4882a593Smuzhiyun 				.fw_name = "gcc_mss_mfab_axis",
46*4882a593Smuzhiyun 			},
47*4882a593Smuzhiyun 			.num_parents = 1,
48*4882a593Smuzhiyun 			.ops = &clk_branch2_ops,
49*4882a593Smuzhiyun 		},
50*4882a593Smuzhiyun 	},
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun static const struct regmap_config mss_regmap_config = {
54*4882a593Smuzhiyun 	.reg_bits	= 32,
55*4882a593Smuzhiyun 	.reg_stride	= 4,
56*4882a593Smuzhiyun 	.val_bits	= 32,
57*4882a593Smuzhiyun 	.fast_io	= true,
58*4882a593Smuzhiyun 	.max_register	= 0x41aa0cc,
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun static struct clk_regmap *mss_sc7180_clocks[] = {
62*4882a593Smuzhiyun 	[MSS_AXI_CRYPTO_CLK] = &mss_axi_crypto_clk.clkr,
63*4882a593Smuzhiyun 	[MSS_AXI_NAV_CLK] = &mss_axi_nav_clk.clkr,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun static const struct qcom_cc_desc mss_sc7180_desc = {
67*4882a593Smuzhiyun 	.config = &mss_regmap_config,
68*4882a593Smuzhiyun 	.clks = mss_sc7180_clocks,
69*4882a593Smuzhiyun 	.num_clks = ARRAY_SIZE(mss_sc7180_clocks),
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
mss_sc7180_probe(struct platform_device * pdev)72*4882a593Smuzhiyun static int mss_sc7180_probe(struct platform_device *pdev)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 	int ret;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
77*4882a593Smuzhiyun 	ret = pm_clk_create(&pdev->dev);
78*4882a593Smuzhiyun 	if (ret)
79*4882a593Smuzhiyun 		goto disable_pm_runtime;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	ret = pm_clk_add(&pdev->dev, "cfg_ahb");
82*4882a593Smuzhiyun 	if (ret < 0) {
83*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to acquire iface clock\n");
84*4882a593Smuzhiyun 		goto destroy_pm_clk;
85*4882a593Smuzhiyun 	}
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	ret = qcom_cc_probe(pdev, &mss_sc7180_desc);
88*4882a593Smuzhiyun 	if (ret < 0)
89*4882a593Smuzhiyun 		goto destroy_pm_clk;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	return 0;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun destroy_pm_clk:
94*4882a593Smuzhiyun 	pm_clk_destroy(&pdev->dev);
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun disable_pm_runtime:
97*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	return ret;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
mss_sc7180_remove(struct platform_device * pdev)102*4882a593Smuzhiyun static int mss_sc7180_remove(struct platform_device *pdev)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	pm_clk_destroy(&pdev->dev);
105*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun static const struct dev_pm_ops mss_sc7180_pm_ops = {
111*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun static const struct of_device_id mss_sc7180_match_table[] = {
115*4882a593Smuzhiyun 	{ .compatible = "qcom,sc7180-mss" },
116*4882a593Smuzhiyun 	{ }
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mss_sc7180_match_table);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun static struct platform_driver mss_sc7180_driver = {
121*4882a593Smuzhiyun 	.probe		= mss_sc7180_probe,
122*4882a593Smuzhiyun 	.remove		= mss_sc7180_remove,
123*4882a593Smuzhiyun 	.driver		= {
124*4882a593Smuzhiyun 		.name		= "sc7180-mss",
125*4882a593Smuzhiyun 		.of_match_table = mss_sc7180_match_table,
126*4882a593Smuzhiyun 		.pm = &mss_sc7180_pm_ops,
127*4882a593Smuzhiyun 	},
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun 
mss_sc7180_init(void)130*4882a593Smuzhiyun static int __init mss_sc7180_init(void)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun 	return platform_driver_register(&mss_sc7180_driver);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun subsys_initcall(mss_sc7180_init);
135*4882a593Smuzhiyun 
mss_sc7180_exit(void)136*4882a593Smuzhiyun static void __exit mss_sc7180_exit(void)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	platform_driver_unregister(&mss_sc7180_driver);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun module_exit(mss_sc7180_exit);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun MODULE_DESCRIPTION("QTI MSS SC7180 Driver");
143*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
144