1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2018, The Linux Foundation. All rights reserved.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/kernel.h>
5*4882a593Smuzhiyun #include <linux/init.h>
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/platform_device.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/clk-provider.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "clk-regmap.h"
14*4882a593Smuzhiyun #include "clk-hfpll.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static const struct hfpll_data hdata = {
17*4882a593Smuzhiyun .mode_reg = 0x00,
18*4882a593Smuzhiyun .l_reg = 0x04,
19*4882a593Smuzhiyun .m_reg = 0x08,
20*4882a593Smuzhiyun .n_reg = 0x0c,
21*4882a593Smuzhiyun .user_reg = 0x10,
22*4882a593Smuzhiyun .config_reg = 0x14,
23*4882a593Smuzhiyun .config_val = 0x430405d,
24*4882a593Smuzhiyun .status_reg = 0x1c,
25*4882a593Smuzhiyun .lock_bit = 16,
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun .user_val = 0x8,
28*4882a593Smuzhiyun .user_vco_mask = 0x100000,
29*4882a593Smuzhiyun .low_vco_max_rate = 1248000000,
30*4882a593Smuzhiyun .min_rate = 537600000UL,
31*4882a593Smuzhiyun .max_rate = 2900000000UL,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static const struct of_device_id qcom_hfpll_match_table[] = {
35*4882a593Smuzhiyun { .compatible = "qcom,hfpll" },
36*4882a593Smuzhiyun { }
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static const struct regmap_config hfpll_regmap_config = {
41*4882a593Smuzhiyun .reg_bits = 32,
42*4882a593Smuzhiyun .reg_stride = 4,
43*4882a593Smuzhiyun .val_bits = 32,
44*4882a593Smuzhiyun .max_register = 0x30,
45*4882a593Smuzhiyun .fast_io = true,
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
qcom_hfpll_probe(struct platform_device * pdev)48*4882a593Smuzhiyun static int qcom_hfpll_probe(struct platform_device *pdev)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct resource *res;
51*4882a593Smuzhiyun struct device *dev = &pdev->dev;
52*4882a593Smuzhiyun void __iomem *base;
53*4882a593Smuzhiyun struct regmap *regmap;
54*4882a593Smuzhiyun struct clk_hfpll *h;
55*4882a593Smuzhiyun struct clk_init_data init = {
56*4882a593Smuzhiyun .num_parents = 1,
57*4882a593Smuzhiyun .ops = &clk_ops_hfpll,
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun * rather than marking the clock critical and forcing the clock
60*4882a593Smuzhiyun * to be always enabled, we make sure that the clock is not
61*4882a593Smuzhiyun * disabled: the firmware remains responsible of enabling this
62*4882a593Smuzhiyun * clock (for more info check the commit log)
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun .flags = CLK_IGNORE_UNUSED,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun int ret;
67*4882a593Smuzhiyun struct clk_parent_data pdata = { .index = 0 };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
70*4882a593Smuzhiyun if (!h)
71*4882a593Smuzhiyun return -ENOMEM;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
74*4882a593Smuzhiyun base = devm_ioremap_resource(dev, res);
75*4882a593Smuzhiyun if (IS_ERR(base))
76*4882a593Smuzhiyun return PTR_ERR(base);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
79*4882a593Smuzhiyun if (IS_ERR(regmap))
80*4882a593Smuzhiyun return PTR_ERR(regmap);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (of_property_read_string_index(dev->of_node, "clock-output-names",
83*4882a593Smuzhiyun 0, &init.name))
84*4882a593Smuzhiyun return -ENODEV;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun init.parent_data = &pdata;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun h->d = &hdata;
89*4882a593Smuzhiyun h->clkr.hw.init = &init;
90*4882a593Smuzhiyun spin_lock_init(&h->lock);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun ret = devm_clk_register_regmap(dev, &h->clkr);
93*4882a593Smuzhiyun if (ret) {
94*4882a593Smuzhiyun dev_err(dev, "failed to register regmap clock: %d\n", ret);
95*4882a593Smuzhiyun return ret;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
99*4882a593Smuzhiyun &h->clkr.hw);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun static struct platform_driver qcom_hfpll_driver = {
103*4882a593Smuzhiyun .probe = qcom_hfpll_probe,
104*4882a593Smuzhiyun .driver = {
105*4882a593Smuzhiyun .name = "qcom-hfpll",
106*4882a593Smuzhiyun .of_match_table = qcom_hfpll_match_table,
107*4882a593Smuzhiyun },
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun module_platform_driver(qcom_hfpll_driver);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
112*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
113*4882a593Smuzhiyun MODULE_ALIAS("platform:qcom-hfpll");
114