1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __QCOM_CLK_HFPLL_H__ 4*4882a593Smuzhiyun #define __QCOM_CLK_HFPLL_H__ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #include <linux/clk-provider.h> 7*4882a593Smuzhiyun #include <linux/spinlock.h> 8*4882a593Smuzhiyun #include "clk-regmap.h" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct hfpll_data { 11*4882a593Smuzhiyun u32 mode_reg; 12*4882a593Smuzhiyun u32 l_reg; 13*4882a593Smuzhiyun u32 m_reg; 14*4882a593Smuzhiyun u32 n_reg; 15*4882a593Smuzhiyun u32 user_reg; 16*4882a593Smuzhiyun u32 droop_reg; 17*4882a593Smuzhiyun u32 config_reg; 18*4882a593Smuzhiyun u32 status_reg; 19*4882a593Smuzhiyun u8 lock_bit; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun u32 droop_val; 22*4882a593Smuzhiyun u32 config_val; 23*4882a593Smuzhiyun u32 user_val; 24*4882a593Smuzhiyun u32 user_vco_mask; 25*4882a593Smuzhiyun unsigned long low_vco_max_rate; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun unsigned long min_rate; 28*4882a593Smuzhiyun unsigned long max_rate; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct clk_hfpll { 32*4882a593Smuzhiyun struct hfpll_data const *d; 33*4882a593Smuzhiyun int init_done; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct clk_regmap clkr; 36*4882a593Smuzhiyun spinlock_t lock; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define to_clk_hfpll(_hw) \ 40*4882a593Smuzhiyun container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun extern const struct clk_ops clk_ops_hfpll; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif 45