1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __QCOM_CLK_ALPHA_PLL_H__ 5*4882a593Smuzhiyun #define __QCOM_CLK_ALPHA_PLL_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/clk-provider.h> 8*4882a593Smuzhiyun #include "clk-regmap.h" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Alpha PLL types */ 11*4882a593Smuzhiyun enum { 12*4882a593Smuzhiyun CLK_ALPHA_PLL_TYPE_DEFAULT, 13*4882a593Smuzhiyun CLK_ALPHA_PLL_TYPE_HUAYRA, 14*4882a593Smuzhiyun CLK_ALPHA_PLL_TYPE_BRAMMO, 15*4882a593Smuzhiyun CLK_ALPHA_PLL_TYPE_FABIA, 16*4882a593Smuzhiyun CLK_ALPHA_PLL_TYPE_TRION, 17*4882a593Smuzhiyun CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 18*4882a593Smuzhiyun CLK_ALPHA_PLL_TYPE_MAX, 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun enum { 22*4882a593Smuzhiyun PLL_OFF_L_VAL, 23*4882a593Smuzhiyun PLL_OFF_CAL_L_VAL, 24*4882a593Smuzhiyun PLL_OFF_ALPHA_VAL, 25*4882a593Smuzhiyun PLL_OFF_ALPHA_VAL_U, 26*4882a593Smuzhiyun PLL_OFF_USER_CTL, 27*4882a593Smuzhiyun PLL_OFF_USER_CTL_U, 28*4882a593Smuzhiyun PLL_OFF_USER_CTL_U1, 29*4882a593Smuzhiyun PLL_OFF_CONFIG_CTL, 30*4882a593Smuzhiyun PLL_OFF_CONFIG_CTL_U, 31*4882a593Smuzhiyun PLL_OFF_CONFIG_CTL_U1, 32*4882a593Smuzhiyun PLL_OFF_TEST_CTL, 33*4882a593Smuzhiyun PLL_OFF_TEST_CTL_U, 34*4882a593Smuzhiyun PLL_OFF_TEST_CTL_U1, 35*4882a593Smuzhiyun PLL_OFF_STATUS, 36*4882a593Smuzhiyun PLL_OFF_OPMODE, 37*4882a593Smuzhiyun PLL_OFF_FRAC, 38*4882a593Smuzhiyun PLL_OFF_CAL_VAL, 39*4882a593Smuzhiyun PLL_OFF_MAX_REGS 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct pll_vco { 45*4882a593Smuzhiyun unsigned long min_freq; 46*4882a593Smuzhiyun unsigned long max_freq; 47*4882a593Smuzhiyun u32 val; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define VCO(a, b, c) { \ 51*4882a593Smuzhiyun .val = a,\ 52*4882a593Smuzhiyun .min_freq = b,\ 53*4882a593Smuzhiyun .max_freq = c,\ 54*4882a593Smuzhiyun } 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /** 57*4882a593Smuzhiyun * struct clk_alpha_pll - phase locked loop (PLL) 58*4882a593Smuzhiyun * @offset: base address of registers 59*4882a593Smuzhiyun * @vco_table: array of VCO settings 60*4882a593Smuzhiyun * @regs: alpha pll register map (see @clk_alpha_pll_regs) 61*4882a593Smuzhiyun * @clkr: regmap clock handle 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun struct clk_alpha_pll { 64*4882a593Smuzhiyun u32 offset; 65*4882a593Smuzhiyun const u8 *regs; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun const struct pll_vco *vco_table; 68*4882a593Smuzhiyun size_t num_vco; 69*4882a593Smuzhiyun #define SUPPORTS_OFFLINE_REQ BIT(0) 70*4882a593Smuzhiyun #define SUPPORTS_FSM_MODE BIT(2) 71*4882a593Smuzhiyun #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 72*4882a593Smuzhiyun u8 flags; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun struct clk_regmap clkr; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /** 78*4882a593Smuzhiyun * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 79*4882a593Smuzhiyun * @offset: base address of registers 80*4882a593Smuzhiyun * @regs: alpha pll register map (see @clk_alpha_pll_regs) 81*4882a593Smuzhiyun * @width: width of post-divider 82*4882a593Smuzhiyun * @post_div_shift: shift to differentiate between odd & even post-divider 83*4882a593Smuzhiyun * @post_div_table: table with PLL odd and even post-divider settings 84*4882a593Smuzhiyun * @num_post_div: Number of PLL post-divider settings 85*4882a593Smuzhiyun * 86*4882a593Smuzhiyun * @clkr: regmap clock handle 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun struct clk_alpha_pll_postdiv { 89*4882a593Smuzhiyun u32 offset; 90*4882a593Smuzhiyun u8 width; 91*4882a593Smuzhiyun const u8 *regs; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct clk_regmap clkr; 94*4882a593Smuzhiyun int post_div_shift; 95*4882a593Smuzhiyun const struct clk_div_table *post_div_table; 96*4882a593Smuzhiyun size_t num_post_div; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct alpha_pll_config { 100*4882a593Smuzhiyun u32 l; 101*4882a593Smuzhiyun u32 alpha; 102*4882a593Smuzhiyun u32 alpha_hi; 103*4882a593Smuzhiyun u32 config_ctl_val; 104*4882a593Smuzhiyun u32 config_ctl_hi_val; 105*4882a593Smuzhiyun u32 config_ctl_hi1_val; 106*4882a593Smuzhiyun u32 user_ctl_val; 107*4882a593Smuzhiyun u32 user_ctl_hi_val; 108*4882a593Smuzhiyun u32 user_ctl_hi1_val; 109*4882a593Smuzhiyun u32 test_ctl_val; 110*4882a593Smuzhiyun u32 test_ctl_hi_val; 111*4882a593Smuzhiyun u32 test_ctl_hi1_val; 112*4882a593Smuzhiyun u32 main_output_mask; 113*4882a593Smuzhiyun u32 aux_output_mask; 114*4882a593Smuzhiyun u32 aux2_output_mask; 115*4882a593Smuzhiyun u32 early_output_mask; 116*4882a593Smuzhiyun u32 alpha_en_mask; 117*4882a593Smuzhiyun u32 alpha_mode_mask; 118*4882a593Smuzhiyun u32 pre_div_val; 119*4882a593Smuzhiyun u32 pre_div_mask; 120*4882a593Smuzhiyun u32 post_div_val; 121*4882a593Smuzhiyun u32 post_div_mask; 122*4882a593Smuzhiyun u32 vco_val; 123*4882a593Smuzhiyun u32 vco_mask; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_ops; 127*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_fixed_ops; 128*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 129*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_postdiv_ops; 130*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_huayra_ops; 131*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_fabia_ops; 134*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 135*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_trion_ops; 138*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_fixed_trion_ops; 139*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_lucid_ops; 142*4882a593Smuzhiyun #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops 143*4882a593Smuzhiyun extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 146*4882a593Smuzhiyun const struct alpha_pll_config *config); 147*4882a593Smuzhiyun void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 148*4882a593Smuzhiyun const struct alpha_pll_config *config); 149*4882a593Smuzhiyun void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 150*4882a593Smuzhiyun const struct alpha_pll_config *config); 151*4882a593Smuzhiyun #define clk_lucid_pll_configure(pll, regmap, config) \ 152*4882a593Smuzhiyun clk_trion_pll_configure(pll, regmap, config) 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #endif 157