1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2018, The Linux Foundation. All rights reserved.
3*4882a593Smuzhiyun #include <linux/clk-provider.h>
4*4882a593Smuzhiyun #include <linux/module.h>
5*4882a593Smuzhiyun #include <linux/platform_device.h>
6*4882a593Smuzhiyun #include <linux/regmap.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "clk-alpha-pll.h"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun static const u8 ipq_pll_offsets[] = {
11*4882a593Smuzhiyun [PLL_OFF_L_VAL] = 0x08,
12*4882a593Smuzhiyun [PLL_OFF_ALPHA_VAL] = 0x10,
13*4882a593Smuzhiyun [PLL_OFF_USER_CTL] = 0x18,
14*4882a593Smuzhiyun [PLL_OFF_CONFIG_CTL] = 0x20,
15*4882a593Smuzhiyun [PLL_OFF_CONFIG_CTL_U] = 0x24,
16*4882a593Smuzhiyun [PLL_OFF_STATUS] = 0x28,
17*4882a593Smuzhiyun [PLL_OFF_TEST_CTL] = 0x30,
18*4882a593Smuzhiyun [PLL_OFF_TEST_CTL_U] = 0x34,
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static struct clk_alpha_pll ipq_pll = {
22*4882a593Smuzhiyun .offset = 0x0,
23*4882a593Smuzhiyun .regs = ipq_pll_offsets,
24*4882a593Smuzhiyun .flags = SUPPORTS_DYNAMIC_UPDATE,
25*4882a593Smuzhiyun .clkr = {
26*4882a593Smuzhiyun .enable_reg = 0x0,
27*4882a593Smuzhiyun .enable_mask = BIT(0),
28*4882a593Smuzhiyun .hw.init = &(struct clk_init_data){
29*4882a593Smuzhiyun .name = "a53pll",
30*4882a593Smuzhiyun .parent_data = &(const struct clk_parent_data) {
31*4882a593Smuzhiyun .fw_name = "xo",
32*4882a593Smuzhiyun },
33*4882a593Smuzhiyun .num_parents = 1,
34*4882a593Smuzhiyun .ops = &clk_alpha_pll_huayra_ops,
35*4882a593Smuzhiyun },
36*4882a593Smuzhiyun },
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static const struct alpha_pll_config ipq_pll_config = {
40*4882a593Smuzhiyun .l = 0x37,
41*4882a593Smuzhiyun .config_ctl_val = 0x04141200,
42*4882a593Smuzhiyun .config_ctl_hi_val = 0x0,
43*4882a593Smuzhiyun .early_output_mask = BIT(3),
44*4882a593Smuzhiyun .main_output_mask = BIT(0),
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const struct regmap_config ipq_pll_regmap_config = {
48*4882a593Smuzhiyun .reg_bits = 32,
49*4882a593Smuzhiyun .reg_stride = 4,
50*4882a593Smuzhiyun .val_bits = 32,
51*4882a593Smuzhiyun .max_register = 0x40,
52*4882a593Smuzhiyun .fast_io = true,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
apss_ipq_pll_probe(struct platform_device * pdev)55*4882a593Smuzhiyun static int apss_ipq_pll_probe(struct platform_device *pdev)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct device *dev = &pdev->dev;
58*4882a593Smuzhiyun struct regmap *regmap;
59*4882a593Smuzhiyun void __iomem *base;
60*4882a593Smuzhiyun int ret;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun base = devm_platform_ioremap_resource(pdev, 0);
63*4882a593Smuzhiyun if (IS_ERR(base))
64*4882a593Smuzhiyun return PTR_ERR(base);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config);
67*4882a593Smuzhiyun if (IS_ERR(regmap))
68*4882a593Smuzhiyun return PTR_ERR(regmap);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
73*4882a593Smuzhiyun if (ret)
74*4882a593Smuzhiyun return ret;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
77*4882a593Smuzhiyun &ipq_pll.clkr.hw);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static const struct of_device_id apss_ipq_pll_match_table[] = {
81*4882a593Smuzhiyun { .compatible = "qcom,ipq6018-a53pll" },
82*4882a593Smuzhiyun { }
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static struct platform_driver apss_ipq_pll_driver = {
87*4882a593Smuzhiyun .probe = apss_ipq_pll_probe,
88*4882a593Smuzhiyun .driver = {
89*4882a593Smuzhiyun .name = "qcom-ipq-apss-pll",
90*4882a593Smuzhiyun .of_match_table = apss_ipq_pll_match_table,
91*4882a593Smuzhiyun },
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun module_platform_driver(apss_ipq_pll_driver);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
96*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
97