1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Qualcomm A53 PLL driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2017, Linaro Limited
6*4882a593Smuzhiyun * Author: Georgi Djakov <georgi.djakov@linaro.org>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "clk-pll.h"
16*4882a593Smuzhiyun #include "clk-regmap.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static const struct pll_freq_tbl a53pll_freq[] = {
19*4882a593Smuzhiyun { 998400000, 52, 0x0, 0x1, 0 },
20*4882a593Smuzhiyun { 1094400000, 57, 0x0, 0x1, 0 },
21*4882a593Smuzhiyun { 1152000000, 62, 0x0, 0x1, 0 },
22*4882a593Smuzhiyun { 1209600000, 63, 0x0, 0x1, 0 },
23*4882a593Smuzhiyun { 1248000000, 65, 0x0, 0x1, 0 },
24*4882a593Smuzhiyun { 1363200000, 71, 0x0, 0x1, 0 },
25*4882a593Smuzhiyun { 1401600000, 73, 0x0, 0x1, 0 },
26*4882a593Smuzhiyun { }
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static const struct regmap_config a53pll_regmap_config = {
30*4882a593Smuzhiyun .reg_bits = 32,
31*4882a593Smuzhiyun .reg_stride = 4,
32*4882a593Smuzhiyun .val_bits = 32,
33*4882a593Smuzhiyun .max_register = 0x40,
34*4882a593Smuzhiyun .fast_io = true,
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
qcom_a53pll_probe(struct platform_device * pdev)37*4882a593Smuzhiyun static int qcom_a53pll_probe(struct platform_device *pdev)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct device *dev = &pdev->dev;
40*4882a593Smuzhiyun struct regmap *regmap;
41*4882a593Smuzhiyun struct resource *res;
42*4882a593Smuzhiyun struct clk_pll *pll;
43*4882a593Smuzhiyun void __iomem *base;
44*4882a593Smuzhiyun struct clk_init_data init = { };
45*4882a593Smuzhiyun int ret;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
48*4882a593Smuzhiyun if (!pll)
49*4882a593Smuzhiyun return -ENOMEM;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
52*4882a593Smuzhiyun base = devm_ioremap_resource(dev, res);
53*4882a593Smuzhiyun if (IS_ERR(base))
54*4882a593Smuzhiyun return PTR_ERR(base);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config);
57*4882a593Smuzhiyun if (IS_ERR(regmap))
58*4882a593Smuzhiyun return PTR_ERR(regmap);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun pll->l_reg = 0x04;
61*4882a593Smuzhiyun pll->m_reg = 0x08;
62*4882a593Smuzhiyun pll->n_reg = 0x0c;
63*4882a593Smuzhiyun pll->config_reg = 0x14;
64*4882a593Smuzhiyun pll->mode_reg = 0x00;
65*4882a593Smuzhiyun pll->status_reg = 0x1c;
66*4882a593Smuzhiyun pll->status_bit = 16;
67*4882a593Smuzhiyun pll->freq_tbl = a53pll_freq;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun init.name = "a53pll";
70*4882a593Smuzhiyun init.parent_names = (const char *[]){ "xo" };
71*4882a593Smuzhiyun init.num_parents = 1;
72*4882a593Smuzhiyun init.ops = &clk_pll_sr2_ops;
73*4882a593Smuzhiyun init.flags = CLK_IS_CRITICAL;
74*4882a593Smuzhiyun pll->clkr.hw.init = &init;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun ret = devm_clk_register_regmap(dev, &pll->clkr);
77*4882a593Smuzhiyun if (ret) {
78*4882a593Smuzhiyun dev_err(dev, "failed to register regmap clock: %d\n", ret);
79*4882a593Smuzhiyun return ret;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
83*4882a593Smuzhiyun &pll->clkr.hw);
84*4882a593Smuzhiyun if (ret) {
85*4882a593Smuzhiyun dev_err(dev, "failed to add clock provider: %d\n", ret);
86*4882a593Smuzhiyun return ret;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static const struct of_device_id qcom_a53pll_match_table[] = {
93*4882a593Smuzhiyun { .compatible = "qcom,msm8916-a53pll" },
94*4882a593Smuzhiyun { }
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, qcom_a53pll_match_table);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static struct platform_driver qcom_a53pll_driver = {
99*4882a593Smuzhiyun .probe = qcom_a53pll_probe,
100*4882a593Smuzhiyun .driver = {
101*4882a593Smuzhiyun .name = "qcom-a53pll",
102*4882a593Smuzhiyun .of_match_table = qcom_a53pll_match_table,
103*4882a593Smuzhiyun },
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun module_platform_driver(qcom_a53pll_driver);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun MODULE_DESCRIPTION("Qualcomm A53 PLL Driver");
108*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
109