1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2012 DENX Software Engineering, GmbH
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Pulled from code:
6*4882a593Smuzhiyun * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
7*4882a593Smuzhiyun * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright 2008 Embedded Alley Solutions, Inc.
10*4882a593Smuzhiyun * Copyright 2009-2011 Freescale Semiconductor, Inc.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/clk.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/device.h>
18*4882a593Smuzhiyun #include <linux/io.h>
19*4882a593Smuzhiyun #include <linux/spi/mxs-spi.h>
20*4882a593Smuzhiyun
mxs_ssp_set_clk_rate(struct mxs_ssp * ssp,unsigned int rate)21*4882a593Smuzhiyun void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun unsigned int ssp_clk, ssp_sck;
24*4882a593Smuzhiyun u32 clock_divide, clock_rate;
25*4882a593Smuzhiyun u32 val;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun ssp_clk = clk_get_rate(ssp->clk);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
30*4882a593Smuzhiyun clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
31*4882a593Smuzhiyun clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
32*4882a593Smuzhiyun if (clock_rate <= 255)
33*4882a593Smuzhiyun break;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (clock_divide > 254) {
37*4882a593Smuzhiyun dev_err(ssp->dev,
38*4882a593Smuzhiyun "%s: cannot set clock to %d\n", __func__, rate);
39*4882a593Smuzhiyun return;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun val = readl(ssp->base + HW_SSP_TIMING(ssp));
45*4882a593Smuzhiyun val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
46*4882a593Smuzhiyun val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
47*4882a593Smuzhiyun val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
48*4882a593Smuzhiyun writel(val, ssp->base + HW_SSP_TIMING(ssp));
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun ssp->clk_rate = ssp_sck;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun dev_dbg(ssp->dev,
53*4882a593Smuzhiyun "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
54*4882a593Smuzhiyun __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);
57