1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include "clk.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /**
13*4882a593Smuzhiyun * struct clk_frac - mxs fractional divider clock
14*4882a593Smuzhiyun * @hw: clk_hw for the fractional divider clock
15*4882a593Smuzhiyun * @reg: register address
16*4882a593Smuzhiyun * @shift: the divider bit shift
17*4882a593Smuzhiyun * @width: the divider bit width
18*4882a593Smuzhiyun * @busy: busy bit shift
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * The clock is an adjustable fractional divider with a busy bit to wait
21*4882a593Smuzhiyun * when the divider is adjusted.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun struct clk_frac {
24*4882a593Smuzhiyun struct clk_hw hw;
25*4882a593Smuzhiyun void __iomem *reg;
26*4882a593Smuzhiyun u8 shift;
27*4882a593Smuzhiyun u8 width;
28*4882a593Smuzhiyun u8 busy;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
32*4882a593Smuzhiyun
clk_frac_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)33*4882a593Smuzhiyun static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
34*4882a593Smuzhiyun unsigned long parent_rate)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct clk_frac *frac = to_clk_frac(hw);
37*4882a593Smuzhiyun u32 div;
38*4882a593Smuzhiyun u64 tmp_rate;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun div = readl_relaxed(frac->reg) >> frac->shift;
41*4882a593Smuzhiyun div &= (1 << frac->width) - 1;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun tmp_rate = (u64)parent_rate * div;
44*4882a593Smuzhiyun return tmp_rate >> frac->width;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
clk_frac_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)47*4882a593Smuzhiyun static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
48*4882a593Smuzhiyun unsigned long *prate)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct clk_frac *frac = to_clk_frac(hw);
51*4882a593Smuzhiyun unsigned long parent_rate = *prate;
52*4882a593Smuzhiyun u32 div;
53*4882a593Smuzhiyun u64 tmp, tmp_rate, result;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (rate > parent_rate)
56*4882a593Smuzhiyun return -EINVAL;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun tmp = rate;
59*4882a593Smuzhiyun tmp <<= frac->width;
60*4882a593Smuzhiyun do_div(tmp, parent_rate);
61*4882a593Smuzhiyun div = tmp;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (!div)
64*4882a593Smuzhiyun return -EINVAL;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun tmp_rate = (u64)parent_rate * div;
67*4882a593Smuzhiyun result = tmp_rate >> frac->width;
68*4882a593Smuzhiyun if ((result << frac->width) < tmp_rate)
69*4882a593Smuzhiyun result += 1;
70*4882a593Smuzhiyun return result;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
clk_frac_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)73*4882a593Smuzhiyun static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate,
74*4882a593Smuzhiyun unsigned long parent_rate)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct clk_frac *frac = to_clk_frac(hw);
77*4882a593Smuzhiyun unsigned long flags;
78*4882a593Smuzhiyun u32 div, val;
79*4882a593Smuzhiyun u64 tmp;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (rate > parent_rate)
82*4882a593Smuzhiyun return -EINVAL;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun tmp = rate;
85*4882a593Smuzhiyun tmp <<= frac->width;
86*4882a593Smuzhiyun do_div(tmp, parent_rate);
87*4882a593Smuzhiyun div = tmp;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (!div)
90*4882a593Smuzhiyun return -EINVAL;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun spin_lock_irqsave(&mxs_lock, flags);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun val = readl_relaxed(frac->reg);
95*4882a593Smuzhiyun val &= ~(((1 << frac->width) - 1) << frac->shift);
96*4882a593Smuzhiyun val |= div << frac->shift;
97*4882a593Smuzhiyun writel_relaxed(val, frac->reg);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun spin_unlock_irqrestore(&mxs_lock, flags);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return mxs_clk_wait(frac->reg, frac->busy);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static const struct clk_ops clk_frac_ops = {
105*4882a593Smuzhiyun .recalc_rate = clk_frac_recalc_rate,
106*4882a593Smuzhiyun .round_rate = clk_frac_round_rate,
107*4882a593Smuzhiyun .set_rate = clk_frac_set_rate,
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
mxs_clk_frac(const char * name,const char * parent_name,void __iomem * reg,u8 shift,u8 width,u8 busy)110*4882a593Smuzhiyun struct clk *mxs_clk_frac(const char *name, const char *parent_name,
111*4882a593Smuzhiyun void __iomem *reg, u8 shift, u8 width, u8 busy)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct clk_frac *frac;
114*4882a593Smuzhiyun struct clk *clk;
115*4882a593Smuzhiyun struct clk_init_data init;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun frac = kzalloc(sizeof(*frac), GFP_KERNEL);
118*4882a593Smuzhiyun if (!frac)
119*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun init.name = name;
122*4882a593Smuzhiyun init.ops = &clk_frac_ops;
123*4882a593Smuzhiyun init.flags = CLK_SET_RATE_PARENT;
124*4882a593Smuzhiyun init.parent_names = (parent_name ? &parent_name: NULL);
125*4882a593Smuzhiyun init.num_parents = (parent_name ? 1 : 0);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun frac->reg = reg;
128*4882a593Smuzhiyun frac->shift = shift;
129*4882a593Smuzhiyun frac->width = width;
130*4882a593Smuzhiyun frac->busy = busy;
131*4882a593Smuzhiyun frac->hw.init = &init;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun clk = clk_register(NULL, &frac->hw);
134*4882a593Smuzhiyun if (IS_ERR(clk))
135*4882a593Smuzhiyun kfree(frac);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return clk;
138*4882a593Smuzhiyun }
139