1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/slab.h>
9*4882a593Smuzhiyun #include "clk.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /**
12*4882a593Smuzhiyun * struct clk_div - mxs integer divider clock
13*4882a593Smuzhiyun * @divider: the parent class
14*4882a593Smuzhiyun * @ops: pointer to clk_ops of parent class
15*4882a593Smuzhiyun * @reg: register address
16*4882a593Smuzhiyun * @busy: busy bit shift
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * The mxs divider clock is a subclass of basic clk_divider with an
19*4882a593Smuzhiyun * addtional busy bit.
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun struct clk_div {
22*4882a593Smuzhiyun struct clk_divider divider;
23*4882a593Smuzhiyun const struct clk_ops *ops;
24*4882a593Smuzhiyun void __iomem *reg;
25*4882a593Smuzhiyun u8 busy;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
to_clk_div(struct clk_hw * hw)28*4882a593Smuzhiyun static inline struct clk_div *to_clk_div(struct clk_hw *hw)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct clk_divider *divider = to_clk_divider(hw);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun return container_of(divider, struct clk_div, divider);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
clk_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)35*4882a593Smuzhiyun static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
36*4882a593Smuzhiyun unsigned long parent_rate)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct clk_div *div = to_clk_div(hw);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return div->ops->recalc_rate(&div->divider.hw, parent_rate);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
clk_div_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)43*4882a593Smuzhiyun static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
44*4882a593Smuzhiyun unsigned long *prate)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct clk_div *div = to_clk_div(hw);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return div->ops->round_rate(&div->divider.hw, rate, prate);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
clk_div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)51*4882a593Smuzhiyun static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
52*4882a593Smuzhiyun unsigned long parent_rate)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct clk_div *div = to_clk_div(hw);
55*4882a593Smuzhiyun int ret;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
58*4882a593Smuzhiyun if (!ret)
59*4882a593Smuzhiyun ret = mxs_clk_wait(div->reg, div->busy);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return ret;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static const struct clk_ops clk_div_ops = {
65*4882a593Smuzhiyun .recalc_rate = clk_div_recalc_rate,
66*4882a593Smuzhiyun .round_rate = clk_div_round_rate,
67*4882a593Smuzhiyun .set_rate = clk_div_set_rate,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
mxs_clk_div(const char * name,const char * parent_name,void __iomem * reg,u8 shift,u8 width,u8 busy)70*4882a593Smuzhiyun struct clk *mxs_clk_div(const char *name, const char *parent_name,
71*4882a593Smuzhiyun void __iomem *reg, u8 shift, u8 width, u8 busy)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct clk_div *div;
74*4882a593Smuzhiyun struct clk *clk;
75*4882a593Smuzhiyun struct clk_init_data init;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun div = kzalloc(sizeof(*div), GFP_KERNEL);
78*4882a593Smuzhiyun if (!div)
79*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun init.name = name;
82*4882a593Smuzhiyun init.ops = &clk_div_ops;
83*4882a593Smuzhiyun init.flags = CLK_SET_RATE_PARENT;
84*4882a593Smuzhiyun init.parent_names = (parent_name ? &parent_name: NULL);
85*4882a593Smuzhiyun init.num_parents = (parent_name ? 1 : 0);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun div->reg = reg;
88*4882a593Smuzhiyun div->busy = busy;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun div->divider.reg = reg;
91*4882a593Smuzhiyun div->divider.shift = shift;
92*4882a593Smuzhiyun div->divider.width = width;
93*4882a593Smuzhiyun div->divider.flags = CLK_DIVIDER_ONE_BASED;
94*4882a593Smuzhiyun div->divider.lock = &mxs_lock;
95*4882a593Smuzhiyun div->divider.hw.init = &init;
96*4882a593Smuzhiyun div->ops = &clk_divider_ops;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun clk = clk_register(NULL, &div->divider.hw);
99*4882a593Smuzhiyun if (IS_ERR(clk))
100*4882a593Smuzhiyun kfree(div);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return clk;
103*4882a593Smuzhiyun }
104