1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Marvell EBU SoC common clock handling 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Marvell 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com> 8*4882a593Smuzhiyun * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9*4882a593Smuzhiyun * Andrew Lunn <andrew@lunn.ch> 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __CLK_MVEBU_COMMON_H_ 14*4882a593Smuzhiyun #define __CLK_MVEBU_COMMON_H_ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <linux/kernel.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun extern spinlock_t ctrl_gating_lock; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct device_node; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct coreclk_ratio { 23*4882a593Smuzhiyun int id; 24*4882a593Smuzhiyun const char *name; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct coreclk_soc_desc { 28*4882a593Smuzhiyun u32 (*get_tclk_freq)(void __iomem *sar); 29*4882a593Smuzhiyun u32 (*get_cpu_freq)(void __iomem *sar); 30*4882a593Smuzhiyun void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); 31*4882a593Smuzhiyun u32 (*get_refclk_freq)(void __iomem *sar); 32*4882a593Smuzhiyun bool (*is_sscg_enabled)(void __iomem *sar); 33*4882a593Smuzhiyun u32 (*fix_sscg_deviation)(u32 system_clk); 34*4882a593Smuzhiyun const struct coreclk_ratio *ratios; 35*4882a593Smuzhiyun int num_ratios; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct clk_gating_soc_desc { 39*4882a593Smuzhiyun const char *name; 40*4882a593Smuzhiyun const char *parent; 41*4882a593Smuzhiyun int bit_idx; 42*4882a593Smuzhiyun unsigned long flags; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun void __init mvebu_coreclk_setup(struct device_node *np, 46*4882a593Smuzhiyun const struct coreclk_soc_desc *desc); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun void __init mvebu_clk_gating_setup(struct device_node *np, 49*4882a593Smuzhiyun const struct clk_gating_soc_desc *desc); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * This function is shared among the Kirkwood, Armada 370, Armada XP 53*4882a593Smuzhiyun * and Armada 375 SoC 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun u32 kirkwood_fix_sscg_deviation(u32 system_clk); 56*4882a593Smuzhiyun #endif 57