1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Marvell Armada 39x SoC clocks
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015 Marvell
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com>
8*4882a593Smuzhiyun * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9*4882a593Smuzhiyun * Andrew Lunn <andrew@lunn.ch>
10*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/clk-provider.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include "common.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * SARL[15] : TCLK frequency
24*4882a593Smuzhiyun * 0 = 250 MHz
25*4882a593Smuzhiyun * 1 = 200 MHz
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * SARH[0] : Reference clock frequency
28*4882a593Smuzhiyun * 0 = 25 Mhz
29*4882a593Smuzhiyun * 1 = 40 Mhz
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define SARL 0
33*4882a593Smuzhiyun #define SARL_A390_TCLK_FREQ_OPT 15
34*4882a593Smuzhiyun #define SARL_A390_TCLK_FREQ_OPT_MASK 0x1
35*4882a593Smuzhiyun #define SARL_A390_CPU_DDR_L2_FREQ_OPT 10
36*4882a593Smuzhiyun #define SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
37*4882a593Smuzhiyun #define SARH 4
38*4882a593Smuzhiyun #define SARH_A390_REFCLK_FREQ BIT(0)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static const u32 armada_39x_tclk_frequencies[] __initconst = {
41*4882a593Smuzhiyun 250000000,
42*4882a593Smuzhiyun 200000000,
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
armada_39x_get_tclk_freq(void __iomem * sar)45*4882a593Smuzhiyun static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun u8 tclk_freq_select;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
50*4882a593Smuzhiyun SARL_A390_TCLK_FREQ_OPT_MASK);
51*4882a593Smuzhiyun return armada_39x_tclk_frequencies[tclk_freq_select];
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static const u32 armada_39x_cpu_frequencies[] __initconst = {
55*4882a593Smuzhiyun [0x0] = 666 * 1000 * 1000,
56*4882a593Smuzhiyun [0x2] = 800 * 1000 * 1000,
57*4882a593Smuzhiyun [0x3] = 800 * 1000 * 1000,
58*4882a593Smuzhiyun [0x4] = 1066 * 1000 * 1000,
59*4882a593Smuzhiyun [0x5] = 1066 * 1000 * 1000,
60*4882a593Smuzhiyun [0x6] = 1200 * 1000 * 1000,
61*4882a593Smuzhiyun [0x8] = 1332 * 1000 * 1000,
62*4882a593Smuzhiyun [0xB] = 1600 * 1000 * 1000,
63*4882a593Smuzhiyun [0xC] = 1600 * 1000 * 1000,
64*4882a593Smuzhiyun [0x12] = 1800 * 1000 * 1000,
65*4882a593Smuzhiyun [0x1E] = 1800 * 1000 * 1000,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
armada_39x_get_cpu_freq(void __iomem * sar)68*4882a593Smuzhiyun static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun u8 cpu_freq_select;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
73*4882a593Smuzhiyun SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
74*4882a593Smuzhiyun if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
75*4882a593Smuzhiyun pr_err("Selected CPU frequency (%d) unsupported\n",
76*4882a593Smuzhiyun cpu_freq_select);
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return armada_39x_cpu_frequencies[cpu_freq_select];
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
86*4882a593Smuzhiyun { .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
87*4882a593Smuzhiyun { .id = A390_CPU_TO_HCLK, .name = "hclk" },
88*4882a593Smuzhiyun { .id = A390_CPU_TO_DCLK, .name = "dclk" },
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
armada_39x_get_clk_ratio(void __iomem * sar,int id,int * mult,int * div)91*4882a593Smuzhiyun static void __init armada_39x_get_clk_ratio(
92*4882a593Smuzhiyun void __iomem *sar, int id, int *mult, int *div)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun switch (id) {
95*4882a593Smuzhiyun case A390_CPU_TO_NBCLK:
96*4882a593Smuzhiyun *mult = 1;
97*4882a593Smuzhiyun *div = 2;
98*4882a593Smuzhiyun break;
99*4882a593Smuzhiyun case A390_CPU_TO_HCLK:
100*4882a593Smuzhiyun *mult = 1;
101*4882a593Smuzhiyun *div = 4;
102*4882a593Smuzhiyun break;
103*4882a593Smuzhiyun case A390_CPU_TO_DCLK:
104*4882a593Smuzhiyun *mult = 1;
105*4882a593Smuzhiyun *div = 2;
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
armada_39x_refclk_ratio(void __iomem * sar)110*4882a593Smuzhiyun static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
113*4882a593Smuzhiyun return 40 * 1000 * 1000;
114*4882a593Smuzhiyun else
115*4882a593Smuzhiyun return 25 * 1000 * 1000;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static const struct coreclk_soc_desc armada_39x_coreclks = {
119*4882a593Smuzhiyun .get_tclk_freq = armada_39x_get_tclk_freq,
120*4882a593Smuzhiyun .get_cpu_freq = armada_39x_get_cpu_freq,
121*4882a593Smuzhiyun .get_clk_ratio = armada_39x_get_clk_ratio,
122*4882a593Smuzhiyun .get_refclk_freq = armada_39x_refclk_ratio,
123*4882a593Smuzhiyun .ratios = armada_39x_coreclk_ratios,
124*4882a593Smuzhiyun .num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
armada_39x_coreclk_init(struct device_node * np)127*4882a593Smuzhiyun static void __init armada_39x_coreclk_init(struct device_node *np)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun mvebu_coreclk_setup(np, &armada_39x_coreclks);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
132*4882a593Smuzhiyun armada_39x_coreclk_init);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun * Clock Gating Control
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
138*4882a593Smuzhiyun { "pex1", NULL, 5 },
139*4882a593Smuzhiyun { "pex2", NULL, 6 },
140*4882a593Smuzhiyun { "pex3", NULL, 7 },
141*4882a593Smuzhiyun { "pex0", NULL, 8 },
142*4882a593Smuzhiyun { "usb3h0", NULL, 9 },
143*4882a593Smuzhiyun { "usb3h1", NULL, 10 },
144*4882a593Smuzhiyun { "sata0", NULL, 15 },
145*4882a593Smuzhiyun { "sdio", NULL, 17 },
146*4882a593Smuzhiyun { "xor0", NULL, 22 },
147*4882a593Smuzhiyun { "xor1", NULL, 28 },
148*4882a593Smuzhiyun { }
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
armada_39x_clk_gating_init(struct device_node * np)151*4882a593Smuzhiyun static void __init armada_39x_clk_gating_init(struct device_node *np)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun mvebu_clk_gating_setup(np, armada_39x_gating_desc);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
156*4882a593Smuzhiyun armada_39x_clk_gating_init);
157