1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Marvell Armada 37xx SoC xtal clocks
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Marvell
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/clk-provider.h>
12*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define NB_GPIO1_LATCH 0x8
17*4882a593Smuzhiyun #define XTAL_MODE BIT(9)
18*4882a593Smuzhiyun
armada_3700_xtal_clock_probe(struct platform_device * pdev)19*4882a593Smuzhiyun static int armada_3700_xtal_clock_probe(struct platform_device *pdev)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
22*4882a593Smuzhiyun const char *xtal_name = "xtal";
23*4882a593Smuzhiyun struct device_node *parent;
24*4882a593Smuzhiyun struct regmap *regmap;
25*4882a593Smuzhiyun struct clk_hw *xtal_hw;
26*4882a593Smuzhiyun unsigned int rate;
27*4882a593Smuzhiyun u32 reg;
28*4882a593Smuzhiyun int ret;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun xtal_hw = devm_kzalloc(&pdev->dev, sizeof(*xtal_hw), GFP_KERNEL);
31*4882a593Smuzhiyun if (!xtal_hw)
32*4882a593Smuzhiyun return -ENOMEM;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun platform_set_drvdata(pdev, xtal_hw);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun parent = np->parent;
37*4882a593Smuzhiyun if (!parent) {
38*4882a593Smuzhiyun dev_err(&pdev->dev, "no parent\n");
39*4882a593Smuzhiyun return -ENODEV;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun regmap = syscon_node_to_regmap(parent);
43*4882a593Smuzhiyun if (IS_ERR(regmap)) {
44*4882a593Smuzhiyun dev_err(&pdev->dev, "cannot get regmap\n");
45*4882a593Smuzhiyun return PTR_ERR(regmap);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun ret = regmap_read(regmap, NB_GPIO1_LATCH, ®);
49*4882a593Smuzhiyun if (ret) {
50*4882a593Smuzhiyun dev_err(&pdev->dev, "cannot read from regmap\n");
51*4882a593Smuzhiyun return ret;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun if (reg & XTAL_MODE)
55*4882a593Smuzhiyun rate = 40000000;
56*4882a593Smuzhiyun else
57*4882a593Smuzhiyun rate = 25000000;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun of_property_read_string_index(np, "clock-output-names", 0, &xtal_name);
60*4882a593Smuzhiyun xtal_hw = clk_hw_register_fixed_rate(NULL, xtal_name, NULL, 0, rate);
61*4882a593Smuzhiyun if (IS_ERR(xtal_hw))
62*4882a593Smuzhiyun return PTR_ERR(xtal_hw);
63*4882a593Smuzhiyun ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, xtal_hw);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return ret;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
armada_3700_xtal_clock_remove(struct platform_device * pdev)68*4882a593Smuzhiyun static int armada_3700_xtal_clock_remove(struct platform_device *pdev)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun of_clk_del_provider(pdev->dev.of_node);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static const struct of_device_id armada_3700_xtal_clock_of_match[] = {
76*4882a593Smuzhiyun { .compatible = "marvell,armada-3700-xtal-clock", },
77*4882a593Smuzhiyun { }
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static struct platform_driver armada_3700_xtal_clock_driver = {
81*4882a593Smuzhiyun .probe = armada_3700_xtal_clock_probe,
82*4882a593Smuzhiyun .remove = armada_3700_xtal_clock_remove,
83*4882a593Smuzhiyun .driver = {
84*4882a593Smuzhiyun .name = "marvell-armada-3700-xtal-clock",
85*4882a593Smuzhiyun .of_match_table = armada_3700_xtal_clock_of_match,
86*4882a593Smuzhiyun },
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun builtin_platform_driver(armada_3700_xtal_clock_driver);
90