1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __MACH_MMP_CLK_RESET_H 3*4882a593Smuzhiyun #define __MACH_MMP_CLK_RESET_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/reset-controller.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define MMP_RESET_INVERT 1 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct mmp_clk_reset_cell { 10*4882a593Smuzhiyun unsigned int clk_id; 11*4882a593Smuzhiyun void __iomem *reg; 12*4882a593Smuzhiyun u32 bits; 13*4882a593Smuzhiyun unsigned int flags; 14*4882a593Smuzhiyun spinlock_t *lock; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct mmp_clk_reset_unit { 18*4882a593Smuzhiyun struct reset_controller_dev rcdev; 19*4882a593Smuzhiyun struct mmp_clk_reset_cell *cells; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifdef CONFIG_RESET_CONTROLLER 23*4882a593Smuzhiyun void mmp_clk_reset_register(struct device_node *np, 24*4882a593Smuzhiyun struct mmp_clk_reset_cell *cells, int nr_resets); 25*4882a593Smuzhiyun #else mmp_clk_reset_register(struct device_node * np,struct mmp_clk_reset_cell * cells,int nr_resets)26*4882a593Smuzhiyunstatic inline void mmp_clk_reset_register(struct device_node *np, 27*4882a593Smuzhiyun struct mmp_clk_reset_cell *cells, int nr_resets) 28*4882a593Smuzhiyun { 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif 33