1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 BayLibre, SAS 4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __G12A_AOCLKC_H 8*4882a593Smuzhiyun #define __G12A_AOCLKC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * CLKID index values 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * These indices are entirely contrived and do not map onto the hardware. 14*4882a593Smuzhiyun * It has now been decided to expose everything by default in the DT header: 15*4882a593Smuzhiyun * include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want 16*4882a593Smuzhiyun * to expose, such as the internal muxes and dividers of composite clocks, 17*4882a593Smuzhiyun * will remain defined here. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define CLKID_AO_SAR_ADC_DIV 17 20*4882a593Smuzhiyun #define CLKID_AO_32K_PRE 20 21*4882a593Smuzhiyun #define CLKID_AO_32K_DIV 21 22*4882a593Smuzhiyun #define CLKID_AO_32K_SEL 22 23*4882a593Smuzhiyun #define CLKID_AO_CEC_PRE 24 24*4882a593Smuzhiyun #define CLKID_AO_CEC_DIV 25 25*4882a593Smuzhiyun #define CLKID_AO_CEC_SEL 26 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define NR_CLKS 29 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #include <dt-bindings/clock/g12a-aoclkc.h> 30*4882a593Smuzhiyun #include <dt-bindings/reset/g12a-aoclkc.h> 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif /* __G12A_AOCLKC_H */ 33